公开(公告)号：US08217671B2

公开(公告)日：2012-07-10

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/00

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US20080284460A1

公开(公告)日：2008-11-20

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/36

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07397259B1

公开(公告)日：2008-07-08

申请号：US11736146

申请日：2007-04-17

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26 ,  G01R33/00 ,  G01R31/02

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columnns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线进行操作的输入/输出引脚。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US20100327892A1

公开(公告)日：2010-12-30

申请号：US12492619

申请日：2009-06-26

申请人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

发明人： Kanak B. Agarwal ,  Peter A. Habitz ,  Jerry D. Hayes ,  Ying Liu ,  Deborah M. Massey ,  Alvin W. Strong

IPC分类号： G01R31/02

CPC分类号： G01R31/2858

摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.

摘要翻译： 提供了一种用于恒流电迁移应力测试的并行阵列架构。 并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。 该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。 此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分 电流源逻辑。 使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

公开(公告)号：US07834649B2

公开(公告)日：2010-11-16

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US20100225348A1

公开(公告)日：2010-09-09

申请号：US12779038

申请日：2010-05-12

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

摘要翻译： 使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。 这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。 通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。 然后通过将表示线性关系的线的斜率除以激励电压来导出电容。 可以对不同的电子设备进行测试，包括晶体管和互连结构。

公开(公告)号：US07782076B2

公开(公告)日：2010-08-24

申请号：US12141862

申请日：2008-06-18

申请人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

发明人： Kanak B. Agarwal ,  Jerry D. Hayes ,  Ying Liu

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/3181 ,  G01R31/3004

摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

公开(公告)号：US07716620B2

公开(公告)日：2010-05-11

申请号：US11682450

申请日：2007-03-06

申请人： Kanak B. Agarwal ,  Ying Liu

发明人： Kanak B. Agarwal ,  Ying Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes include peak, rms and average current, which can be used in subsequent reliability analyses. Interconnect path nodes are traversed and circuit moments are either retrieved from a previous interconnect delay analysis or are computed. For each pair of nodes, current moments are computed from the circuit moments. The average current is computed from the zero-order circuit moment and the peak and rms currents are obtained from expressions according to a lognormal or other distribution shape assumption for the current waveform at each node.

摘要翻译： 用于评估集成电路中金属层瞬态电流的基于瞬时的方法和系统提供了通过金属层中的每个互连的瞬态电流幅度的计算有效的评估。 可确定的幅度包括峰值，有效值和平均电流，可用于后续的可靠性分析。 互连路径节点被遍历，并且从先前的互连延迟分析中检索电路时刻，或者被计算。 对于每对节点，从电路时刻计算当前时刻。 平均电流是从零阶电路力矩计算的，峰值和均方根电流根据每个节点上的电流波形的对数正态分布形状假设的表达式获得。

公开(公告)号：US20070296442A1

公开(公告)日：2007-12-27

申请号：US11422913

申请日：2006-06-08

申请人： Kanak B. Agarwal ,  Ying Liu ,  Chandler T. McDowell ,  Sani R. Nassif ,  James F. Plusquellic ,  Jayakumaran Sivagnaname

发明人： Kanak B. Agarwal ,  Ying Liu ,  Chandler T. McDowell ,  Sani R. Nassif ,  James F. Plusquellic ,  Jayakumaran Sivagnaname

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G11C11/41 ,  G11C29/02 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

摘要翻译： 用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。 该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。 每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。 该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。

公开(公告)号：US07408372B2

公开(公告)日：2008-08-05

申请号：US11422913

申请日：2006-06-08

申请人： Kanak B. Agarwal ,  Ying Liu ,  Chandler T. McDowell ,  Sani R. Nassif ,  James F. Plusquellic ,  Jayakumaran Sivagnaname

发明人： Kanak B. Agarwal ,  Ying Liu ,  Chandler T. McDowell ,  Sani R. Nassif ,  James F. Plusquellic ,  Jayakumaran Sivagnaname

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G11C11/41 ,  G11C29/02 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

摘要翻译： 用于局部器件不匹配的统计表征的测试结构包含布置在行/列可寻址阵列中的密集填充的SRAM器件，其使许多器件的资源共享。 该测试结构包括一个校准或消除误差源的内置感测机构，以及电流转向，以避免杂散路径上的电流泄漏的负面影响。 每列的栅极和漏极线都从顶部和底部驱动以最小化寄生效应。 该系统可以处理大量设备，同时仍然提供高空间分辨率的电流测量。