Invention Grant
- Patent Title: MOS transistor characteristic detection apparatus and CMOS circuit characteristic automatic adjustment apparatus
- Patent Title (中): MOS晶体管特性检测装置和CMOS电路特性自动调节装置
-
Application No.: US11723234Application Date: 2007-03-19
-
Publication No.: US07397265B2Publication Date: 2008-07-08
- Inventor: Osamu Taketoshi , Sadahiro Watanabe
- Applicant: Osamu Taketoshi , Sadahiro Watanabe
- Applicant Address: JP Osaka
- Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2006-077313 20060320
- Main IPC: G01R31/26
- IPC: G01R31/26

Abstract:
A CMOS circuit characteristic automatic adjustment apparatus includes a replica signal generation circuit for generating a replica signal capable of minimizing a drain voltage of an MOS transistor in a target circuit, a replica circuit for receiving the replica signal, voltage buffers for receiving respective drain voltages of MOS transistors in the target circuit and the replica circuit, respectively, MOS transistors for receiving respective output voltages of the voltage buffers, a comparison circuit for comparing respective sizes of currents flowing in the MOS transistors, respectively, and an adjustment circuit for adjusting, based on a comparison result, operation states of the target circuit and the replica circuit.
Public/Granted literature
Information query