公开(公告)号：US07624295B2

公开(公告)日：2009-11-24

申请号：US10971122

申请日：2004-10-25

Applicant: Osamu Taketoshi ,  Isao Tanaka ,  Toru Wada

Inventor： Osamu Taketoshi ,  Isao Tanaka ,  Toru Wada

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3885 ,  Y02D10/126

Abstract: To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.

Abstract translation: 为了降低包括多个处理器的处理器系统在不降低处理能力的情况下的功耗，CPU检测添加到指令代码的模式设置信息，并将时钟控制信号和电源电压控制信号输出到时钟控制部分和 电源电压控制部分。 当多个处理引擎并行执行指令时，提供频率低于预定频率的时钟信号和低于预定电压的电源电压。 结果，降低功耗并且通过并行执行维持处理能力。

公开(公告)号：US06411241B1

公开(公告)日：2002-06-25

申请号：US09517622

申请日：2000-03-03

Applicant: Osamu Taketoshi

Inventor： Osamu Taketoshi

IPC: H03M112

CPC classification number: H03M1/002 ,  H03M1/007 ,  H03M1/167 ,  H03M1/208

Abstract: An A/D converter guarantees high conversion precision and reduces power consumption not only in a standby state but in any other states. Therefore, a subtraction circuit is added to the A/D converter obtain a difference between a reference voltage and an analog signal, and an analog signal stored as a reference voltage is used. The difference is converted only by an A/D conversion unit for converting lower bits, and an operation mode for stopping the operation of an idle conversion unit is designed, thereby to perform an analog-to-digital converting operation.

Abstract translation: A / D转换器保证高转换精度，并且不仅在待机状态，而且在任何其他状态下都能降低功耗。 因此，减法电路被添加到A / D转换器获得参考电压和模拟信号之间的差异，并且使用作为参考电压存储的模拟信号。 该差异仅由用于转换较低位的A / D转换单元转换，并且设计用于停止空转转单元的操作的操作模式，从而进行模数转换操作。

公开(公告)号：US07397265B2

公开(公告)日：2008-07-08

申请号：US11723234

申请日：2007-03-19

Applicant: Osamu Taketoshi ,  Sadahiro Watanabe

Inventor： Osamu Taketoshi ,  Sadahiro Watanabe

IPC: G01R31/26

CPC classification number: G01R31/2621

Abstract: A CMOS circuit characteristic automatic adjustment apparatus includes a replica signal generation circuit for generating a replica signal capable of minimizing a drain voltage of an MOS transistor in a target circuit, a replica circuit for receiving the replica signal, voltage buffers for receiving respective drain voltages of MOS transistors in the target circuit and the replica circuit, respectively, MOS transistors for receiving respective output voltages of the voltage buffers, a comparison circuit for comparing respective sizes of currents flowing in the MOS transistors, respectively, and an adjustment circuit for adjusting, based on a comparison result, operation states of the target circuit and the replica circuit.

Abstract translation: CMOS电路特性自动调整装置包括：复制信号生成电路，用于生成能够使目标电路中的MOS晶体管的漏极电压最小化的复制信号;复制电路，用于接收复制信号;电压缓冲器，用于接收各自的漏极电压 目标电路中的MOS晶体管和复制电路分别用于接收电压缓冲器的各个输出电压的MOS晶体管，分别用于比较在MOS晶体管中流动的电流的各自的尺寸的比较电路和用于调整的调整电路 在比较结果中，目标电路和复制电路的操作状态。

公开(公告)号：US20070216439A1

公开(公告)日：2007-09-20

申请号：US11723234

申请日：2007-03-19

Applicant: Osamu Taketoshi ,  Sadahiro Watanabe

Inventor： Osamu Taketoshi ,  Sadahiro Watanabe

IPC: G01R31/26

CPC classification number: G01R31/2621

Abstract: A CMOS circuit characteristic automatic adjustment apparatus includes a replica signal generation circuit for generating a replica signal capable of minimizing a drain voltage of an MOS transistor in a target circuit, a replica circuit for receiving the replica signal, voltage buffers for receiving respective drain voltages of MOS transistors in the target circuit and the replica circuit, respectively, MOS transistors for receiving respective output voltages of the voltage buffers, a comparison circuit for comparing respective sizes of currents flowing in the MOS transistors, respectively, and an adjustment circuit for adjusting, based on a comparison result, operation states of the target circuit and the replica circuit.

Abstract translation: CMOS电路特性自动调整装置包括：复制信号生成电路，用于生成能够使目标电路中的MOS晶体管的漏极电压最小化的复制信号;复制电路，用于接收复制信号;电压缓冲器，用于接收各自的漏极电压 目标电路中的MOS晶体管和复制电路分别用于接收电压缓冲器的各个输出电压的MOS晶体管，分别用于比较在MOS晶体管中流动的电流的各自的尺寸的比较电路和用于调整的调整电路 在比较结果中，目标电路和复制电路的操作状态。

公开(公告)号：US20050102560A1

公开(公告)日：2005-05-12

申请号：US10971122

申请日：2004-10-25

Applicant: Osamu Taketoshi ,  Isao Tanaka ,  Toru Wada

Inventor： Osamu Taketoshi ,  Isao Tanaka ,  Toru Wada

IPC: G06F1/32 ,  G06F1/04 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F11/00 ,  G06F15/76

CPC classification number: G06F1/3203 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3885 ,  Y02D10/126

Abstract: To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code and outputs a clock control signal and a power supply voltage control signal to a clock controlling section and a power supply voltage controlling section, respectively. When a plurality of processing engines execute an instruction in parallel, clock signals with a frequency lower than a predetermined frequency and power supply voltages lower than a predetermined voltage are supplied. As a result, power consumption is reduced and the processing ability is maintained by the parallel execution.

Abstract translation: 为了降低包括多个处理器的处理器系统在不降低处理能力的情况下的功耗，CPU检测添加到指令代码的模式设置信息，并将时钟控制信号和电源电压控制信号输出到时钟控制部分和 电源电压控制部分。 当多个处理引擎并行执行指令时，提供频率低于预定频率的时钟信号和低于预定电压的电源电压。 结果，降低功耗并且通过并行执行维持处理能力。

公开(公告)号：US5389898A

公开(公告)日：1995-02-14

申请号：US79530

申请日：1993-06-22

Applicant: Osamu Taketoshi ,  Tsuguyasu Hatsuda ,  Seiji Yamaguchi

Inventor： Osamu Taketoshi ,  Tsuguyasu Hatsuda ,  Seiji Yamaguchi

IPC: H03L7/089 ,  H03L7/099 ,  H03L7/10 ,  H03L7/183 ,  H03L7/18

CPC classification number: H03L7/089 ,  H03L7/099 ,  H03L7/0997 ,  H03L7/10 ,  H03L7/183

Abstract: The invention discloses a PLL formed by a phase detector, a filter, three VCO's (VCO1, VCO2, and VCO3), a multiplexer, and a frequency divider. The VCO1, VCO2, and VCO3 have different mean frequencies, each oscillating at a frequency controlled according to the voltage value of a phase control signal from the filter. The multiplexer selects one of the VCO's which operate in parallel. If a pulse of a digital phase difference signal UP indicating that an internal signal is delayed in phase with respect to a reference signal is output twice in succession, or if a pulse of a digital phase difference signal DOWN indicating that an internal signal is advanced in phase with respect to a reference signal is output twice in succession, a counter makes the multiplexer change its current VCO selection via a shift register. Accordingly, high-speed PLL pulling is achievable even if a PLL frequency variable-range is expanded.

Abstract translation: 本发明公开了一种由相位检测器，滤波器，三个VCO（VCO1，VCO2和VCO3），多路复用器和分频器组成的PLL。 VCO1，VCO2和VCO3具有不同的平均频率，每个频率在根据来自滤波器的相位控制信号的电压值控制的频率下振荡。 复用器选择并行操作的VCO中的一个。 如果相对于参考信号指示内部信号相位延迟的数字相位差信号UP的脉冲连续输出两次，或者如果指示内部信号提前的数字相位差信号DOWN的脉冲 相对于参考信号的相位被连续输出两次，计数器使多路复用器通过移位寄存器改变其当前的VCO选择。 因此，即使PLL频率可变范围扩大，也可以实现高速PLL拉动。