发明授权
- 专利标题: Method and apparatus for efficient utilization for prescient instruction prefetch
- 专利标题(中): 有效利用预编程指令预取的方法和装置
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申请号: US10658072申请日: 2003-09-08
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公开(公告)号: US07404067B2公开(公告)日: 2008-07-22
- 发明人: Tor M. Aamodt , Hong Wang , Per Hammarlund , John P. Shen , Steve Shih-wei Liao , Perry H. Wang
- 申请人: Tor M. Aamodt , Hong Wang , Per Hammarlund , John P. Shen , Steve Shih-wei Liao , Perry H. Wang
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理商 Shireen I. Bacon
- 主分类号: G06F9/38
- IPC分类号: G06F9/38 ; G06F9/46
摘要:
Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.