公开(公告)号：US08887174B2

公开(公告)日：2014-11-11

申请号：US13191317

申请日：2011-07-26

Applicant: Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

Inventor： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

IPC: G06F3/00 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Abstract translation: 监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。 本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少 减少与用户级线程相关联的性能抑制事件。

公开(公告)号：US20140115594A1

公开(公告)日：2014-04-24

申请号：US14067223

申请日：2013-10-30

Applicant: Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

Inventor： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC: G06F9/48

CPC classification number: G06F9/4843

Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。

公开(公告)号：US20120017221A1

公开(公告)日：2012-01-19

申请号：US13191317

申请日：2011-07-26

Applicant: Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

Inventor： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

IPC: G06F9/46

CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

Abstract: A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Abstract translation: 监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。 本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少 减少与用户级线程相关联的性能抑制事件。

公开(公告)号：US20100332811A1

公开(公告)日：2010-12-30

申请号：US12879898

申请日：2010-09-10

Applicant: Hong Wang ,  Tor M. Aamodt ,  Pedro Marcuello ,  Jared W. Stark, IV ,  John P. Shen ,  Antonio Gonzalez ,  Per Hammarlund ,  Gerolf F. Hoflehner ,  Perry H. Wang ,  Steve Shih-wei Liao

Inventor： Hong Wang ,  Tor M. Aamodt ,  Pedro Marcuello ,  Jared W. Stark, IV ,  John P. Shen ,  Antonio Gonzalez ,  Per Hammarlund ,  Gerolf F. Hoflehner ,  Perry H. Wang ,  Steve Shih-wei Liao

IPC: G06F9/38

CPC classification number: G06F9/4843 ,  G06F8/433 ,  G06F9/3009 ,  G06F9/3808 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3851

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract translation: 通过使用同时提供的线程来减少与检索主线程的指令信息相关的延迟。 辅助线程是用于为主线程执行指令预取和/或跟踪预构建的推测性预取线程。

公开(公告)号：US07844801B2

公开(公告)日：2010-11-30

申请号：US10632431

申请日：2003-07-31

Applicant: Hong Wang ,  Perry H. Wang ,  Jeffery A. Brown ,  Per Hammarlund ,  George Z. Chrysos ,  Doron Orenstein ,  Steve Shih-wei Liao ,  John P. Shen

Inventor： Hong Wang ,  Perry H. Wang ,  Jeffery A. Brown ,  Per Hammarlund ,  George Z. Chrysos ,  Doron Orenstein ,  Steve Shih-wei Liao ,  John P. Shen

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/3842 ,  G06F9/383 ,  G06F9/3851 ,  G06F12/0862

Abstract: Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.

Abstract translation: 提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。 数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。 由辅助线程预取的数据被提供给辅助核心。 对于一个实施例，由辅助线程预取的数据被推送到主核心。 它也可以也可以不被提供给辅助核心。 在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。 对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

公开(公告)号：US07424576B2

公开(公告)日：2008-09-09

申请号：US09891523

申请日：2001-06-27

Applicant: Ryan N. Rakvic ,  John P. Shen ,  Deepak Limaye

Inventor： Ryan N. Rakvic ,  John P. Shen ,  Deepak Limaye

IPC: G06F12/00

CPC classification number: G06F12/0864 ,  G06F12/0897

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Abstract translation: 为微处理器中的高速缓存提供并行缓存。 缓存可以独立地寻址。 高速缓存的级别可以在单个周期中接受多个加载请求，并将每个加载请求应用于相应的缓存。 根据存储在每个cachelet中的内容，该cachelet可以产生对相应加载请求的命中/未命中响应。 可能会满足打入其缓存的加载请求。 加载丢失其cachelet的请求可能被称为另一个缓存级别。

公开(公告)号：US07404067B2

公开(公告)日：2008-07-22

申请号：US10658072

申请日：2003-09-08

Applicant: Tor M. Aamodt ,  Hong Wang ,  Per Hammarlund ,  John P. Shen ,  Steve Shih-wei Liao ,  Perry H. Wang

Inventor： Tor M. Aamodt ,  Hong Wang ,  Per Hammarlund ,  John P. Shen ,  Steve Shih-wei Liao ,  Perry H. Wang

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3842 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859

Abstract: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

Abstract translation: 装置，系统和方法的实施例通过一个或多个推测性线程增强在指令预取期间处理器资源利用的效率。 利用重命名逻辑和映射表来对推测性线程指令流中的指令进行滤波。 映射表包括一个肯定事件位，用于指示相关联的物理寄存器的内容是否反映由主线程计算的值。 线程进度信标表用于跟踪主线程和推测式辅助线程的相对进度。 基于线程进度信标表中的信息，主线程可能会影响不太可能为主线程提供性能优势的辅助线程的终止。

公开(公告)号：US07398521B2

公开(公告)日：2008-07-08

申请号：US10779193

申请日：2004-02-13

Applicant: Gerolf F. Hoflehner ,  Shih-wei Liao ,  Xinmin Tian ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

Inventor： Gerolf F. Hoflehner ,  Shih-wei Liao ,  Xinmin Tian ,  Hong Wang ,  Daniel M. Lavery ,  Perry Wang ,  Dongkeun Kim ,  Milind Girkar ,  John P. Shen

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

Abstract translation: 本文描述了用于多线程的线程管理的方法和装置。 在一个实施例中，示例性过程包括在具有在数据处理系统中可执行的一个或多个线程的代码的编译期间选择具有最低阶的当前线程，确定分配给从当前线程产生的一个或多个子线程的资源， 并且考虑分配给当前线程的一个或多个子线程的资源来为当前线程分配资源，以避免当前线程与其一个或多个子线程之间的资源冲突。 还描述了其它方法和装置。

公开(公告)号：US20160019067A1

公开(公告)日：2016-01-21

申请号：US14866875

申请日：2015-09-26

Applicant: Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

Inventor： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US20110264866A1

公开(公告)日：2011-10-27

申请号：US13175928

申请日：2011-07-04

Applicant: Quinn A. Jacobson ,  Anne Weinberger Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham N. Chinya ,  Bratin Saba ,  Ali-Reza Adl-Tabatabai ,  Gad S. Sheaffer

Inventor： Quinn A. Jacobson ,  Anne Weinberger Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham N. Chinya ,  Bratin Saba ,  Ali-Reza Adl-Tabatabai ,  Gad S. Sheaffer

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F11/3471 ,  G06F11/3648 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/145 ,  G06F2201/865

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Abstract translation: 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。