发明授权
- 专利标题： Stacked multi-gate transistor design and method of fabrication
- 专利标题（中）： 堆叠多栅晶体管的设计与制作方法
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申请号： US11395860申请日： 2006-03-31
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公开(公告)号： US07407847B2公开(公告)日： 2008-08-05
- 发明人: Brian S Doyle , Titash Rakshit , Robert S Chau , Suman Datta , Justin K Brask , Uday Shah
- 申请人： Brian S Doyle , Titash Rakshit , Robert S Chau , Suman Datta , Justin K Brask , Uday Shah
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： H01L21/84
- IPC分类号： H01L21/84
摘要：
A multi-body thickness (MBT) field effect transistor (FET) comprises a silicon body formed on a substrate. The silicon body may comprise a wide section and a narrow section between the wide section and the substrate. The silicon body may comprise more than one pair of a wide section and a narrow section, each pair being located at a different height of the silicon body. The silicon body is surrounded by a gate material on three sides. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The MBT-FET combines the advantages of a wide fin device and a narrow fin device.