发明授权
US07410858B2 Isolation structure configurations for modifying stresses in semiconductor devices
有权
用于修改半导体器件中的应力的隔离结构配置
- 专利标题: Isolation structure configurations for modifying stresses in semiconductor devices
- 专利标题(中): 用于修改半导体器件中的应力的隔离结构配置
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申请号: US11437379申请日: 2006-05-19
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公开(公告)号: US07410858B2公开(公告)日: 2008-08-12
- 发明人: Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
- 申请人: Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: H01L29/72
- IPC分类号: H01L29/72
摘要:
An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.