公开(公告)号：US07425458B2

公开(公告)日：2008-09-16

申请号：US11184521

申请日：2005-07-19

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： G01R31/31718 ,  G01R31/31723 ,  H01L23/50 ,  H01L23/5382 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In an embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such as a logic network, whose operational characteristic(s) is predicted to be and is actually identified as sub-optimal through IC testing, particularly following a process change, a mask shrink, operation of the IC at higher clock frequency, or the like. Expensive redesign is avoided by selectively coupling capacitors into the IC circuit element as needed, under control of selector logic that is responsive to control signals. Methods of operation, as well as application of the apparatus to an electronic assembly and an electronic system, are also described.

摘要翻译： 可选择的电容器用于修改集成电路（IC）的功能电路元件的性能特征。 在一个实施例中，去耦电容器被实现为IC表面上的附加或替代的安装焊盘。 为每个IC电路元件（例如逻辑网络）提供至少一个可选择的电容器，其逻辑网络的操作特性被预测为并且实际上通过IC测试被识别为次优，特别是在过程变化之后，掩模收缩 ，在较高时钟频率下操作IC等。 在根据控制信号响应的选择器逻辑的控制下，通过选择性地将电容器耦合到IC电路元件中来避免昂贵的重新设计。 还描述了操作方法以及将装置应用于电子组件和电子系统。

公开(公告)号：US20070013023A1

公开(公告)日：2007-01-18

申请号：US11525982

申请日：2006-09-22

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L29/00

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

摘要翻译： 一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。 根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度 用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

公开(公告)号：US06937458B2

公开(公告)日：2005-08-30

申请号：US10726050

申请日：2003-12-02

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/50 ,  H01L23/538 ,  H01L23/58 ,  H01G4/10

CPC分类号： G01R31/31718 ,  G01R31/31723 ,  H01L23/50 ,  H01L23/5382 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Selectable capacitors are used to modify performance characteristics of functional circuit elements of an integrated circuit (IC). In one embodiment, the decoupling capacitors are implemented as additional or alternative mounting pads on a surface of the IC. At least one selectable capacitor is provided for each IC circuit element, such as a logic network, whose operational characteristic(s) is predicted to be and is actually identified as sub-optimal through IC testing, particularly following a process change, a mask shrink, operation of the IC at higher clock frequency, or the like. Expensive redesign is avoided by selectively coupling capacitors into the IC circuit element as needed, under control of selector logic that is responsive to control signals. Methods of operation, as well as application of the apparatus to an electronic assembly and an electronic system, are also described.

摘要翻译： 可选择的电容器用于修改集成电路（IC）的功能电路元件的性能特征。 在一个实施例中，去耦电容器被实现为IC表面上的附加或替代安装焊盘。 为每个IC电路元件（例如逻辑网络）提供至少一个可选择的电容器，其逻辑网络的操作特性被预测为并通过IC测试被实际识别为次优，特别是在过程变化之后，掩模收缩 ，在较高时钟频率下操作IC等。 在根据控制信号响应的选择器逻辑的控制下，通过选择性地将电容器耦合到IC电路元件中来避免昂贵的重新设计。 还描述了操作方法以及将装置应用于电子组件和电子系统。

公开(公告)号：US20050158980A1

公开(公告)日：2005-07-21

申请号：US11056324

申请日：2005-02-10

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/485 ,  H01L21/44

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00

摘要： The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying bond pad.

摘要翻译： 本发明公开了一种用于I / O的具有分段BLM的设备的新颖布局和过程。 在第一实施例中，每个BLM被分成两个段。 这些片段彼此靠近并连接到相同的上覆凸起。 在第二实施例中，每个BLM被分成多于两个段。 在第三实施例中，每个段电连接到多于一个的底层通孔。 在第四实施例中，每个段电连接到多于一个的底层接合焊盘。

公开(公告)号：US20050070119A1

公开(公告)日：2005-03-31

申请号：US10675587

申请日：2003-09-29

申请人： Theodore Doros ,  Krishna Seshan

发明人： Theodore Doros ,  Krishna Seshan

IPC分类号： B81B3/00 ,  H01L21/30 ,  H01L21/31 ,  H03H3/04 ,  H04B7/26 ,  H04Q7/22

CPC分类号： B81B3/0072 ,  B81C2201/0109

摘要： Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick and thin regions of materials. The weight-compensating/tuning layer includes narrow and wide regions corresponding to the thick and thin regions, respectively.

摘要翻译： 本发明的实施例在其表面拓扑变化的结构（例如，具有一层或多层材料的硅晶片（例如膜））上形成体重补偿/调谐层。 表面拓扑的变化采取厚薄的材料区域的形式。 重量补偿/调谐层分别包括对应于厚和薄区域的窄且宽的区域。

公开(公告)号：US06162652A

公开(公告)日：2000-12-19

申请号：US1969

申请日：1997-12-31

申请人： M. Lawrence A. Dass ,  Amir Roggel ,  Krishna Seshan

发明人： M. Lawrence A. Dass ,  Amir Roggel ,  Krishna Seshan

IPC分类号： G01R1/067 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/44

CPC分类号： H01L24/05 ,  G01R1/06733 ,  G01R31/2884 ,  G01R31/2886 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05027 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of testing an integrated circuit device including depositing a solder bump on a surface of a bond pad on an integrated circuit device, heat treating the solder bump, and testing the integrated circuit device by probing the solder bump.

摘要翻译： 一种测试集成电路器件的方法，包括在集成电路器件上的接合焊盘的表面上沉积焊料凸块，热处理焊料凸块，以及通过探测焊料凸块来测试集成电路器件。

公开(公告)号：US6143668A

公开(公告)日：2000-11-07

申请号：US941795

申请日：1997-09-30

申请人： M. Lawrence A. Dass ,  Kenneth D. Karklin ,  Krishna Seshan ,  Amir Roggel

发明人： M. Lawrence A. Dass ,  Kenneth D. Karklin ,  Krishna Seshan ,  Amir Roggel

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/31

CPC分类号： H01L24/03 ,  H01L24/11 ,  H01L21/76802 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13099 ,  H01L2224/48227 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S438/958

摘要： A method of exposing a bond pad includes: providing an integrated circuit having a bond pad, a first passivation layer overlying an area portion of the bond pad, and a second passivation layer overlying the first passivation layer; removing a portion of the second passivation layer above the area portion of the bond pad exposing an area of the first passivation layer; curing the second passivation; and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit. A probe card is further disclosed, including a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.

摘要翻译： 暴露接合焊盘的方法包括：提供具有接合焊盘的集成电路，覆盖接合焊盘的区域部分的第一钝化层和覆盖第一钝化层的第二钝化层; 去除接合焊盘的区域部分上方的第二钝化层的暴露第一钝化层的区域的部分; 固化第二次钝化; 以及蚀刻所述第一钝化层的所述暴露区域的一部分以暴露所述接合焊盘的顶表面。 还公开了将集成电路芯片耦合到芯片封装的方法，这是一种探测集成电路的焊盘的方法。 还公开了一种探针卡，包括耦合到印刷电路板的探针组件，探针组件具有倾斜的侧壁部分，其具有从侧壁部分延伸的多个探测光束。

公开(公告)号：US6137143A

公开(公告)日：2000-10-24

申请号：US107351

申请日：1998-06-30

申请人： Sanjay Dabral ,  Krishna Seshan

发明人： Sanjay Dabral ,  Krishna Seshan

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0255 ,  H01L2924/0002

摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

摘要翻译： 一种集成电路，其包括占用集成电路基板的第一区域的性能电路和耦合到所述性能电路并且占据与所述第一区域分离的集成电路基板的第二区域的保护电路。 此外，形成集成电路的方法包括以下步骤：形成占据集成电路基板的第一区域的性能电路，形成与第一区域分离的占据集成电路的第二区域的保护电路，以及耦合保护 电路到性能电路。

公开(公告)号：US5504434A

公开(公告)日：1996-04-02

申请号：US453590

申请日：1995-05-30

申请人： Dominic J. Schepis ,  Krishna Seshan

发明人： Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/48 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14 ,  H01L21/485 ,  H01L22/22

摘要： A measurement technique and instrument using rectangular pulse trains of differing repetition rates and synchronously operated lock-in amplifiers to reject electrical noise and capture changes in resistance and capacitance of an electrical element even during a short electrical pulse applied thereto or in the presence of high levels of electrical noise. Particular applications are for electrical programming of fuses and repair of conductors by material deposition.

摘要翻译： 使用不同重复率的矩形脉冲串和同步操作的锁定放大器的测量技术和仪器，以抵抗电气噪声，并捕获电子元件的电阻和电容的变化，即使在施加到其上的短电脉冲中或存在高电平 的电噪声。 特殊应用是用于熔丝的电气编程和通过材料沉积修复导体。

公开(公告)号：US07250333B2

公开(公告)日：2007-07-31

申请号：US10394977

申请日：2003-03-20

申请人： Sanjay Dabral ,  Krishna Seshan

发明人： Sanjay Dabral ,  Krishna Seshan

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。