发明授权
- 专利标题： Memory module and memory system
- 专利标题（中）： 内存模块和内存系统
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申请号： US11634405申请日： 2006-12-06
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公开(公告)号： US07411806B2公开(公告)日： 2008-08-12
- 发明人: Seiji Funaba , Yoji Nishio , Kayoko Shibata
- 申请人： Seiji Funaba , Yoji Nishio , Kayoko Shibata
- 申请人地址： JP Tokyo
- 专利权人： Elpida Memory, Inc.
- 当前专利权人： Elpida Memory, Inc.
- 当前专利权人地址： JP Tokyo
- 代理机构： Katten Muchin Rosenman LLP
- 优先权： JP2002-222771 20020731
- 主分类号： G11C5/06
- IPC分类号： G11C5/06 ; G11C5/02
摘要：
A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.
公开/授权文献
- US20070081376A1 Memory module and memory system 公开/授权日：2007-04-12
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