Invention Grant
- Patent Title: Nonvolatile semiconductor memory device
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Application No.: US11701404Application Date: 2007-02-02
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Publication No.: US07411834B2Publication Date: 2008-08-12
- Inventor: Yoshihiko Kusakabe , Kenichi Oto , Satoshi Kawasaki
- Applicant: Yoshihiko Kusakabe , Kenichi Oto , Satoshi Kawasaki
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2006-027010 20060203
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G11C16/04

Abstract:
A sub-decoder element provided corresponding to each word line is constructed by the same conductive type MOS transistors. The sub-decoder elements are arranged in a plurality of columns such that the layout of active regions for forming the sub-decoder elements is inverted in a Y direction and displaced by one sub-decoder element in an X direction. The arrangement of the sub-decoder elements is adjusted such that high voltage is not applied to both of gate electrodes adjacent in the Y direction. A well voltage of a well region for forming the sub-decoder element group is set to a voltage level such that a source to substrate of the transistor of the sub-decoder element is set into a deep reversed-bias state. In a nonvolatile semiconductor memory device, the leakage by a parasitic MOS in a sub-decoder circuit or word line driving circuit to which a positive or negative high voltage is supplied, can be suppressed.
Public/Granted literature
- US20070183213A1 Nonvolatile semiconductor memory device Public/Granted day:2007-08-09
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