发明授权
- 专利标题： Layout method for miniaturized memory array area
- 专利标题（中）： 微型化存储器阵列区域的布局方法
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申请号： US10875572申请日： 2004-06-25
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公开(公告)号： US07418685B2公开(公告)日： 2008-08-26
- 发明人: Yuko Watanabe , Koji Arai , Seiji Narui
- 申请人： Yuko Watanabe , Koji Arai , Seiji Narui
- 申请人地址： JP Tokyo JP Tokyo JP Tokyo
- 专利权人： Elpida Memory, Inc.,Hitachi Ulsi Systems, Co., Ltd.,Hitachi Ltd.
- 当前专利权人： Elpida Memory, Inc.,Hitachi Ulsi Systems, Co., Ltd.,Hitachi Ltd.
- 当前专利权人地址： JP Tokyo JP Tokyo JP Tokyo
- 代理机构： Sughrue Mion, PLLC
- 优先权： JP2003-184012 20030627
- 主分类号： G06F9/455
- IPC分类号： G06F9/455 ; G06F17/50
摘要：
Bit lines and a pair of two tungsten wires having the same widths are formed at a portion where a through-hole is to be formed such that the bit lines and the tungsten wires are arranged at regular intervals. A through-hole for connection to another wiring layer is formed between the tungsten wires. A connection wiring made of tungsten is formed over the through-hole so as to have a predetermined margin around the through-hole. In a photolithography process, a slit having a small width enough to be insensitive to a photo-resist is formed so as to span the through-hole.
公开/授权文献
- US20050028125A1 Layout method for miniaturized memory array area 公开/授权日：2005-02-03
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