公开(公告)号：US08659321B2

公开(公告)日：2014-02-25

申请号：US13306560

申请日：2011-11-29

Applicant: Yuko Watanabe ,  Yoshiro Riho ,  Hiromasa Noda ,  Yoji Idei ,  Kosuke Goto

Inventor： Yuko Watanabe ,  Yoshiro Riho ,  Hiromasa Noda ,  Yoji Idei ,  Kosuke Goto

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076

Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

Abstract translation: 半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及 用于控制第一至第三驱动器电路的操作的定时控制电路。 定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。 延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为 基于第一和第二延迟电路的延迟量的总和来决定。

公开(公告)号：US07414874B2

公开(公告)日：2008-08-19

申请号：US11588328

申请日：2006-10-27

Applicant: Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

Inventor： Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

IPC: G11C5/02

CPC classification number: H01L27/105 ,  G11C5/025 ,  G11C11/4097

Abstract: Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Abstract translation: 公开了一种半导体存储器件，包括存储单元阵列块和沿着第一方向布置有存储单元阵列块的电路区域。 电路区域包括沿第一方向布置有第一区域的第一区域和第二区域。 第一区域设置有在垂直于第一方向的第二方向上排列的第一电路和第二电路。 第二区域设置有沿第二方向排列的多个第三电路。

公开(公告)号：US20070096156A1

公开(公告)日：2007-05-03

申请号：US11588328

申请日：2006-10-27

Applicant: Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

Inventor： Hiroki Fujisawa ,  Isamu Fujii ,  Yuko Watanabe

IPC: H01L27/10

CPC classification number: H01L27/105 ,  G11C5/025 ,  G11C11/4097

Abstract: Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.

Abstract translation: 公开了一种半导体存储器件，包括存储单元阵列块和沿着第一方向布置有存储单元阵列块的电路区域。 电路区域包括沿第一方向布置有第一区域的第一区域和第二区域。 第一区域设置有在垂直于第一方向的第二方向上排列的第一电路和第二电路。 第二区域设置有沿第二方向排列的多个第三电路。

公开(公告)号：US20070003685A1

公开(公告)日：2007-01-04

申请号：US11476665

申请日：2006-06-29

Applicant: Yuko Watanabe

Inventor： Yuko Watanabe

IPC: A23L2/00

CPC classification number: A23L2/52 ,  A23G3/48 ,  A23L33/105

Abstract: The present invention is to provide a novel prostacyclin production-increasing agent, a blood flow enhancer, a prophylaxis or improvement agent of blood flow disorder, or a skin improving agent, each of which comprises an elderberry extract as an effective ingredient, and foods, medicaments or cosmetics containing the same.

Abstract translation: 本发明提供一种新陈代谢前列环酸生产增加剂，血流增强剂，血液流动障碍的预防或改善剂或皮肤改善剂，其中每种包含接骨木提取物作为有效成分，以及食品， 含有相同的药物或化妆品。

公开(公告)号：US20070002450A1

公开(公告)日：2007-01-04

申请号：US11500985

申请日：2006-08-09

Applicant: Yuko Watanabe ,  Takashi Sakamoto ,  Hiroyuki Taira ,  Seigou Nakai

Inventor： Yuko Watanabe ,  Takashi Sakamoto ,  Hiroyuki Taira ,  Seigou Nakai

IPC: G02B27/00

CPC classification number: G02B27/0025

Abstract: An imaging optics capable of compensating for chromatic aberration is provided with a light shielding means in a surface peripheral area of a certain lens element in a lens system so as to block a light flux of a specified wavelength range, thereby eliminating chromatic aberration in halo of the light flux of the specified wavelength range when it passes the periphery of the lens system. Thus, the invention provides the imaging optics that, without an increase in the number of pieces of lens elements and without a use of an expensive specified low-dispersion glass material, in contrast with the prior art imaging optics of the same optical performances, well compensates for chromatic aberration, especially, in halo.

Abstract translation: 能够补偿色像差的成像光学元件在透镜系统中的特定透镜元件的表面周边区域中设置有遮光装置，以阻挡特定波长范围的光束，从而消除光晕中的色差 当通过透镜系统的周边时，指定波长范围的光通量。 因此，本发明提供了成像光学器件，与现有技术的相同光学性能的成像光学器件相比，在不增加透镜元件数量并且不使用昂贵的指定的低分散玻璃材料的情况下， 补偿色差，特别是在光晕中。

公开(公告)号：US20120133399A1

公开(公告)日：2012-05-31

申请号：US13306560

申请日：2011-11-29

Applicant: Yuko WATANABE ,  Yoshiro RIHO ,  Hiromasa NODA ,  Yoji IDEI ,  Kosuke GOTO

Inventor： Yuko WATANABE ,  Yoshiro RIHO ,  Hiromasa NODA ,  Yoji IDEI ,  Kosuke GOTO

IPC: H03K3/00

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076

Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

Abstract translation: 半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及 用于控制第一至第三驱动器电路的操作的定时控制电路。 定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。 延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为 基于第一和第二延迟电路的延迟量的总和来决定。

公开(公告)号：US08014081B2

公开(公告)日：2011-09-06

申请号：US11500985

申请日：2006-08-09

Applicant: Yuko Watanabe ,  Takashi Sakamoto ,  Hiroyuki Taira ,  Seigou Nakai

Inventor： Yuko Watanabe ,  Takashi Sakamoto ,  Hiroyuki Taira ,  Seigou Nakai

IPC: G02B9/08

CPC classification number: G02B27/0025

Abstract: An imaging optics capable of compensating for chromatic aberration is provided with a light shielding means in a surface peripheral area of a certain lens element in a lens system so as to block a light flux of a specified wavelength range, thereby eliminating chromatic aberration in halo of the light flux of the specified wavelength range when it passes the periphery of the lens system. Thus, the invention provides the imaging optics that, without an increase in the number of pieces of lens elements and without a use of an expensive specified low-dispersion glass material, in contrast with the prior art imaging optics of the same optical performances, well compensates for chromatic aberration, especially, in halo.

Abstract translation: 能够补偿色像差的成像光学元件在透镜系统中的特定透镜元件的表面周边区域中设置有遮光装置，以阻挡特定波长范围的光束，从而消除光晕中的色差 当通过透镜系统的周边时，指定波长范围的光通量。 因此，本发明提供了成像光学器件，与现有技术的相同光学性能的成像光学器件相比，在不增加透镜元件数量并且不使用昂贵的指定的低分散玻璃材料的情况下， 补偿色差，特别是在光晕中。

公开(公告)号：US20110074945A1

公开(公告)日：2011-03-31

申请号：US12891483

申请日：2010-09-27

Applicant: Yuko Watanabe ,  Yoko Saito ,  Tomoko Kobayashi ,  Koichi Shintani

Inventor： Yuko Watanabe ,  Yoko Saito ,  Tomoko Kobayashi ,  Koichi Shintani

IPC: H04N5/225

CPC classification number: H04N5/23203 ,  H04N5/232 ,  H04N5/23241 ,  H04N5/23245 ,  H04N7/183

Abstract: An imaging apparatus includes an imaging unit for capturing a subject and generating image data of the subject, an operation input unit for receiving inputs of operation signals containing a release signal for instructing the imaging unit to shoot, an acceleration detector for detecting an acceleration of the imaging apparatus, a state detector for separately detecting a case in which the imaging apparatus is overland, a case in which the imaging apparatus is underwater and a photographer shoots while swimming, and a case in which the imaging apparatus is underwater and the photographer shoots while changing a water depth, and a control unit for performing operation control depending on an input into the operation input unit and/or into the acceleration detector according to a state detection result by the state detector.

Abstract translation: 一种成像装置，包括：拍摄对象并生成被摄体的图像数据的摄像部;操作输入部，接收包含用于指示拍摄部拍摄的释放信号的动作信号的输入;加速度检测部， 成像装置，用于分别检测成像装置是陆地的情况的状态检测器，成像装置在水中的情况和摄影者在游泳时拍摄的情况，以及拍摄装置在水下并且拍摄者拍摄的情况 改变水深;以及控制单元，用于根据状态检测器的状态检测结果，根据对操作输入单元的输入和/或进入加速度检测器进行操作控制。

公开(公告)号：US20090108376A1

公开(公告)日：2009-04-30

申请号：US12259527

申请日：2008-10-28

Applicant: Isamu FUJII ,  Shinichi MIYATAKE ,  Yuko WATANABE ,  Homare SATO

Inventor： Isamu FUJII ,  Shinichi MIYATAKE ,  Yuko WATANABE ,  Homare SATO

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  H01L27/10885

Abstract: A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.

Abstract translation: 半导体器件包括以预定间距排列的多条信号线; 连接到信号线的第一和第二MOS晶体管，并且彼此串联连接; 以及连接装置，其作为串联连接的第一和第二MOS晶体管之间的连接节点，并且将第一和第二MOS晶体管之一的源极区域连接到第一和第二MOS晶体管的另一个的漏极区域，经由 通过绝缘层形成的接触孔和连接到接触孔的导电层。

公开(公告)号：US07412223B1

公开(公告)日：2008-08-12

申请号：US09720729

申请日：2000-05-15

Applicant: Masaaki Yamamoto ,  Yuko Watanabe ,  Kouji Chiba ,  Masaharu Nakatsuchi

Inventor： Masaaki Yamamoto ,  Yuko Watanabe ,  Kouji Chiba ,  Masaharu Nakatsuchi

IPC: H04Q7/20

CPC classification number: H04L29/06 ,  H04L67/04 ,  H04L67/06 ,  H04L67/42 ,  H04L69/329 ,  H04M1/72561 ,  H04M3/428 ,  H04M2201/38

Abstract: A transmission-reception device receives site screen data transmitted from an IP server. An SRAM records the site screen data received by the transmission-reception device. When in a reception standby state, the CPU reads the site screen data recorded in the SRAM, generates a site screen, and displays this on the liquid crystal display.

Abstract translation: 发送接收装置接收从IP服务器发送的站点屏幕数据。 SRAM记录由发送接收装置接收到的现场画面数据。 当处于接收待机状态时，CPU读取记录在SRAM中的站点屏幕数据，生成站点屏幕，并将其显示在液晶显示器上。