Invention Grant
US07422950B2 Strained silicon MOS device with box layer between the source and drain regions
有权
应变硅MOS器件,在源极和漏极区之间具有盒层
- Patent Title: Strained silicon MOS device with box layer between the source and drain regions
- Patent Title (中): 应变硅MOS器件,在源极和漏极区之间具有盒层
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Application No.: US11304351Application Date: 2005-12-14
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Publication No.: US07422950B2Publication Date: 2008-09-09
- Inventor: Giuseppe Curello , Hemant V. Deshpande , Sunit Tyagi , Mark Bohr
- Applicant: Giuseppe Curello , Hemant V. Deshpande , Sunit Tyagi , Mark Bohr
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Rahul D. Engineer
- Main IPC: H01L21/84
- IPC: H01L21/84

Abstract:
A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
Public/Granted literature
- US20070134859A1 Strained silicon MOS device with box layer between the source and drain regions Public/Granted day:2007-06-14
Information query
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