Invention Grant
- Patent Title: Semiconductor memory device capable of controlling potential level of power supply line and/or ground line
- Patent Title (中): 能够控制电源线和/或接地线的电位的半导体存储器件
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Application No.: US11889393Application Date: 2007-08-13
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Publication No.: US07423916B2Publication Date: 2008-09-09
- Inventor: Koji Nii
- Applicant: Koji Nii
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2003-161115 20030605
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G11C7/10 ; G11C11/00

Abstract:
Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.
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