发明授权
US07432192B2 Post ECP multi-step anneal/H2 treatment to reduce film impurity
有权
后期ECP多步退火/ H2处理以降低膜杂质
- 专利标题: Post ECP multi-step anneal/H2 treatment to reduce film impurity
- 专利标题(中): 后期ECP多步退火/ H2处理以降低膜杂质
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申请号: US11347946申请日: 2006-02-06
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公开(公告)号: US07432192B2公开(公告)日: 2008-10-07
- 发明人: Hsien-Ping Feng , Jung-Chih Tsao , Hsi-Kuei Cheng , Chih-Tsung Lee , Ming-Yuan Cheng , Steven Lin , Ray Chuang , Chi-Wen Liu
- 申请人: Hsien-Ping Feng , Jung-Chih Tsao , Hsi-Kuei Cheng , Chih-Tsung Lee , Ming-Yuan Cheng , Steven Lin , Ray Chuang , Chi-Wen Liu
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company
- 当前专利权人: Taiwan Semiconductor Manufacturing Company
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Duane Morris LLP
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.
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