公开(公告)号：US07667835B2

公开(公告)日：2010-02-23

申请号：US11510951

申请日：2006-08-28

申请人： Hsi-Kuei Cheng ,  Jung-Chih Tsao ,  Hsien-Ping Feng ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang

发明人： Hsi-Kuei Cheng ,  Jung-Chih Tsao ,  Hsien-Ping Feng ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang

IPC分类号： G01N21/00 ,  G01N21/55 ,  G01B11/28 ,  C25D21/12 ,  H01L21/00

CPC分类号： C25D17/00 ,  C25D7/123 ,  C25D17/001 ,  C25D21/12 ,  G01N21/55 ,  G01N2021/8411 ,  H01L21/67005 ,  H01L21/67253

摘要： An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

摘要翻译： 公开了一种用于防止电镀金属从晶片剥离的装置和方法。 该装置包括具有光源和反射率检测器的种子层检测器系统。 根据该方法，光源将光束发射到晶片上，反射率检测器接收从晶片反射的光。 测量晶片表面的反射率以确定晶片上晶种层的存在或不存在，以及种子层是否具有用于最佳电镀金属到籽晶层上的最小厚度。

公开(公告)号：US07432192B2

公开(公告)日：2008-10-07

申请号：US11347946

申请日：2006-02-06

申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层超过沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。

公开(公告)号：US20080047827A1

公开(公告)日：2008-02-28

申请号：US11510951

申请日：2006-08-28

申请人： Hsi-Kuei Cheng ,  Jung-Chih Tsao ,  Hsien-Ping Feng ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang

发明人： Hsi-Kuei Cheng ,  Jung-Chih Tsao ,  Hsien-Ping Feng ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang

IPC分类号： C25B9/00

CPC分类号： C25D17/00 ,  C25D7/123 ,  C25D17/001 ,  C25D21/12 ,  G01N21/55 ,  G01N2021/8411 ,  H01L21/67005 ,  H01L21/67253

摘要： An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

摘要翻译： 公开了一种用于防止电镀金属从晶片剥离的装置和方法。 该装置包括具有光源和反射率检测器的种子层检测器系统。 根据该方法，光源将光束发射到晶片上，反射率检测器接收从晶片反射的光。 测量晶片表面的反射率以确定晶片上晶种层的存在或不存在，以及种子层是否具有用于最佳电镀金属到籽晶层上的最小厚度。

公开(公告)号：US07252750B2

公开(公告)日：2007-08-07

申请号：US10664347

申请日：2003-09-16

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Ke-Wei Chen ,  Ying-Lang Wang

IPC分类号： C25D17/00

CPC分类号： C25D5/48 ,  C25D5/028 ,  Y10S204/07

摘要： A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.

摘要翻译： 用于接触晶片的图案化表面的双接触环和在晶片的图案化中心区域上的金属的电化学电镀，并从晶片的外边缘区域移除金属。 双接触环具有与晶片的外部边缘区域接触的外部电压环和与晶片的内部中心区域接触的内部电压环。 外部电压环连接到正电压源，内部电压环连接到负电压源。 内部电压环向晶片施加负电压以便于将金属电镀到晶片的图案化区域上。 通过外部电压环将正电压施加到晶片，以从衬底的外部边缘区域去除镀覆的金属。

公开(公告)号：US07199045B2

公开(公告)日：2007-04-03

申请号：US10854061

申请日：2004-05-26

申请人： Chi Wen Liu ,  Jung Chih Tsao ,  Shih Tzung Chang ,  Ying Lang Wang ,  Kei Wei Chen

发明人： Chi Wen Liu ,  Jung Chih Tsao ,  Shih Tzung Chang ,  Ying Lang Wang ,  Kei Wei Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/76877

摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

摘要翻译： 在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。 导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。 导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

公开(公告)号：US07189650B2

公开(公告)日：2007-03-13

申请号：US10987713

申请日：2004-11-12

申请人： Chi-Wen Liu ,  Hsien-Ping Feng ,  Jung-Chih Tsao

发明人： Chi-Wen Liu ,  Hsien-Ping Feng ,  Jung-Chih Tsao

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885

摘要： The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing a second copper film and annealing the second copper film for a duration of time to remove impurities. The second copper film can be deposited by electrochemical plating without HCl/C-based additive. The second copper film can also be deposited by sputtering to avoid impurities including C, Cl and S.

摘要翻译： 本发明涉及一种通过两步沉积来提高铜膜质量的方法和装置。 两级沉积可以包括通过电化学电镀沉积第一铜膜，在所需温度下将第一铜膜退火一段时间以除去任何杂质，沉积第二铜膜并使第二铜膜退火一段时间 去除杂质。 第二个铜膜可以通过不含HCl / C基添加剂的电化学电镀沉积。 也可以通过溅射沉积第二铜膜以避免包括C，Cl和S在内的杂质。

公开(公告)号：US20050255642A1

公开(公告)日：2005-11-17

申请号：US10842454

申请日：2004-05-11

申请人： Chi-Wen Liu ,  Jung-Chih Tsao

发明人： Chi-Wen Liu ,  Jung-Chih Tsao

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L21/338 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/49

CPC分类号： H01L21/76885 ,  H01L21/28079 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66583

摘要： A method of fabricating an inlaid structure. A sacrificial layer having a trench opening over a substrate is provided. A metal layer is deposited over the sacrificial layer filling the trench openings. A first CMP is performed to remove excess metal layer above the sacrificial layer to form an interconnect structure. The sacrificial layer is removed to expose the interconnect structure. A first dielectric layer is deposited over the substrate covering the interconnect structure. A second CMP is performed on the first dielectric layer to planarize the first dielectric layer.

摘要翻译： 一种制造镶嵌结构的方法。 提供了在衬底上具有沟槽开口的牺牲层。 在填充沟槽开口的牺牲层上沉积金属层。 执行第一CMP以去除牺牲层上方的多余金属层以形成互连结构。 去除牺牲层以露出互连结构。 在覆盖互连结构的衬底上沉积第一介电层。 在第一电介质层上执行第二CMP以使第一电介质层平坦化。

公开(公告)号：US20050118808A1

公开(公告)日：2005-06-02

申请号：US10724201

申请日：2003-12-01

申请人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

发明人： Chi-Wen Liu ,  Jung-Chih Tsao ,  Shien-Ping Feng ,  Kei-Wei Chen ,  Shih-Chi Lin ,  Ray Chuang

IPC分类号： H01L21/302 ,  H01L21/321 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

摘要翻译： 降低CMP工艺中图案效果的方法。 该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。 还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

公开(公告)号：US20100230815A1

公开(公告)日：2010-09-16

申请号：US12785618

申请日：2010-05-24

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

IPC分类号： H01L23/522 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.

摘要翻译： 半导体器件及其制造方法。 示例性器件包括衬底，电介质层，保护层和共形阻挡层。 电介质层覆盖在衬底上并且包括开口。 开口包括下部和较宽的上部，暴露基底的部分。 上部的底部作为开口的肩部。 保护层覆盖开口的至少一个肩部。 共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

公开(公告)号：US07417321B2

公开(公告)日：2008-08-26

申请号：US11323484

申请日：2005-12-30

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

摘要翻译： 通过半导体产品互连的结构和工艺流程。 提供底部金属层以表示半导体产品中的连接层。 底部金属层上的隔离层包括露出底部金属层的一部分的通孔。 通孔包括侧壁和底部。 第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。 在通孔的底部和第一阻挡金属层上形成金属底层。 在金属底层上形成第二阻挡金属层。 金属填充层填充通孔。 金属底层和第二阻挡金属层之间的晶格失配小于约5％。