发明授权
- 专利标题: Method for manufacturing semiconductor device
- 专利标题(中): 制造半导体器件的方法
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申请号: US11123248申请日: 2005-05-06
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公开(公告)号: US07439137B2公开(公告)日: 2008-10-21
- 发明人: Hiroyasu Ishida , Hirotoshi Kubo , Shouji Miyahara , Masato Onda
- 申请人: Hiroyasu Ishida , Hirotoshi Kubo , Shouji Miyahara , Masato Onda
- 申请人地址: JP Osaka
- 专利权人: Sanyo Electric Co., Ltd.
- 当前专利权人: Sanyo Electric Co., Ltd.
- 当前专利权人地址: JP Osaka
- 代理机构: Morrison & Foerster LLP
- 优先权: JP2004-142389 20040512
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.
公开/授权文献
- US20050255706A1 Method for manufacturing semiconductor device 公开/授权日:2005-11-17
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