发明授权
US07447073B2 Method for handling a defective top gate of a source-side injection flash memory array
有权
用于处理源侧注入闪存阵列的有缺陷的顶栅的方法
- 专利标题： Method for handling a defective top gate of a source-side injection flash memory array
- 专利标题（中）： 用于处理源侧注入闪存阵列的有缺陷的顶栅的方法
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申请号： US11707341申请日： 2007-02-16
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公开(公告)号： US07447073B2公开(公告)日： 2008-11-04
- 发明人: Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
- 申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
- 申请人地址： US CA Sunnyvale
- 专利权人： Silicon Storage Technology, Inc.
- 当前专利权人： Silicon Storage Technology, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： DLA Piper US LLP
- 主分类号： G11C16/34
- IPC分类号： G11C16/34
摘要：
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
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