发明授权
US07456099B2 Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices
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形成用于减小半导体器件中横向边缘电容的结构的方法
- 专利标题： Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices
- 专利标题（中）： 形成用于减小半导体器件中横向边缘电容的结构的方法
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申请号： US11420253申请日： 2006-05-25
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公开(公告)号： US07456099B2公开(公告)日： 2008-11-25
- 发明人: Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
- 申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Cantor Colburn LLP
- 代理商 Lisa U. Jaklitsch
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763 ; H01L21/44
摘要：
A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
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