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    MOSFET including asymmetric source and drain regions
    2.
    发明授权
    MOSFET including asymmetric source and drain regions 失效
    MOSFET包括不对称的源极和漏极区域

    公开(公告)号：US08772874B2

    公开(公告)日：2014-07-08

    申请号：US13216554

    申请日：2011-08-24

    申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/66045 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66803 ,  H01L29/785

    摘要： At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.

    摘要翻译： 作为平面FET或鳍式FET的结构的场效应晶体管（FET）结构的至少一个漏极侧表面在结构上被惰性或电活性掺杂剂的成角度的离子注入损坏，而至少一个 保护晶体管的源极侧表面不被栅极堆叠和栅极间隔物的注入。 半导体材料的外延生长在至少一个结构损坏的漏极侧表面上延迟，而外延生长在至少一个源极侧表面上没有延迟。 凸起的外延源区域具有比凸起的外延漏极区域更大的厚度，从而提供具有比漏极侧外部电阻更小的源极侧外部电阻并且具有比源极重叠电容更少的漏极侧重叠电容的非对称FET。

    Reducing gate resistance in nonplanar multi-gate transistor
    3.
    发明授权
    Reducing gate resistance in nonplanar multi-gate transistor 失效
    降低非平面多栅极晶体管的栅极电阻

    公开(公告)号：US08604546B1

    公开(公告)日：2013-12-10

    申请号：US13544176

    申请日：2012-07-09

    申请人： Andres Bryant ,  Theodorus E. Standaert ,  Gen Tsutsui ,  Chun-Chen Yeh

    发明人： Andres Bryant ,  Theodorus E. Standaert ,  Gen Tsutsui ,  Chun-Chen Yeh

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7845

    摘要： A semiconductor transistor structure has a plurality of fins, a cap on the center portion of the top of each of the fins, a conductive liner lining the cap and the sidewalls of the center portion of the fins, and an insulator between the center portions of the fins. The insulator contacts the conductive liner, and the fins extend further from the surface of the substrate relative to an amount the insulator extends from the surface of the substrate. The structure further includes a conductive layer positioned on the insulator between the center portions of the fins and positioned between the cap of the fins. The conductive layer contacts the conductive liner.

    摘要翻译： 半导体晶体管结构具有多个散热片，在每个翅片的顶部的中心部分上的盖，衬套盖的导电衬垫和散热片的中心部分的侧壁以及中心部分之间的绝缘体 翅片 绝缘体接触导电衬垫，并且散热片相对于绝缘体从衬底的表面延伸的量从衬底的表面进一步延伸。 所述结构还包括位于所述绝缘体之间的导电层，所述导电层位于所述翅片的中心部分之间并且位于所述翅片的帽之间。 导电层接触导电衬垫。

    FINFET WITH MERGED FINS AND VERTICAL SILICIDE
    6.
    发明申请
    FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
    具有合并的FINS和垂直硅胶的FINFET

    公开(公告)号：US20130161744A1

    公开(公告)日：2013-06-27

    申请号：US13337874

    申请日：2011-12-27

    申请人： Veeraraghavan S. BASKER ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    发明人： Veeraraghavan S. BASKER ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

    IPC分类号： H01L27/12 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/41791 ,  H01L29/66795

    摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.

    摘要翻译： 提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于 翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。 翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。 硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

    MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS
    7.
    发明申请
    MULTI-GATE FIELD-EFFECT TRANSISTORS WITH VARIABLE FIN HEIGHTS 审中-公开

    公开(公告)号：US20130082333A1

    公开(公告)日：2013-04-04

    申请号：US13610385

    申请日：2012-09-11

    申请人： Hsueh-Chung Chen ,  Su Chen Fan ,  Theodorus E. Standaert ,  Chun-Chen Yeh

    发明人： Hsueh-Chung Chen ,  Su Chen Fan ,  Theodorus E. Standaert ,  Chun-Chen Yeh

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823431 ,  H01L27/0886

    摘要： Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position.

    SOI FinFET with recessed merged Fins and liner for enhanced stress coupling
    10.
    发明授权
    SOI FinFET with recessed merged Fins and liner for enhanced stress coupling 失效
    SOI FinFET具有凹入的合并Fins和衬垫，用于增强应力耦合

    公开(公告)号：US08445334B1

    公开(公告)日：2013-05-21

    申请号：US13330746

    申请日：2011-12-20

    申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

    发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Effendi Leobandung ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/7843 ,  H01L29/6656 ,  H01L29/66795

    摘要： FinFETS and methods for making FinFETs with a recessed stress liner. A method includes providing an SOI substrate with fins, forming a gate over the fins, forming an off-set spacer on the gate, epitaxially growing a film to merge the fins, depositing a dummy spacer around the gate, and recessing the merged epi film. Silicide is then formed on the recessed merged epi film followed by deposition of a stress liner film over the FinFET. By using a recessed merged epi process, a MOSFET with a vertical silicide (i.e. perpendicular to the substrate) can be formed. The perpendicular silicide improves spreading resistance.

    摘要翻译： FinFET和用于制造具有凹陷应力衬垫的FinFET的方法。 一种方法包括向SOI衬底提供翅片，在鳍片上形成栅极，在栅极上形成偏置间隔物，外延生长膜以合并鳍片，在栅极周围沉积虚拟间隔物，并使合并的膜片膜凹陷 。 然后在凹陷的合并epi膜上形成硅化物，然后在FinFET上沉积应力衬垫膜。 通过使用凹入的合并epi工艺，可以形成具有垂直硅化物（即垂直于衬底）的MOSFET。 垂直硅化物提高了耐扩散性。