If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.