发明授权
US07467256B2 Processor having content addressable memory for block-based queue structures
有权
具有内容可寻址存储器的处理器，用于基于块的队列结构
- 专利标题： Processor having content addressable memory for block-based queue structures
- 专利标题（中）： 具有内容可寻址存储器的处理器，用于基于块的队列结构
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申请号： US11027601申请日： 2004-12-28
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公开(公告)号： US07467256B2公开(公告)日： 2008-12-16
- 发明人: Sanjeev Jain , Gilbert M. Wolrich , Debra Bernstein
- 申请人： Sanjeev Jain , Gilbert M. Wolrich , Debra Bernstein
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Daly, Crowley, Mofford & Durkee, LLP
- 主分类号： G06F12/00
- IPC分类号： G06F12/00
摘要：
Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.
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