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    QUEUE ARRAYS IN NETWORK DEVICES
    1.
    发明申请
    QUEUE ARRAYS IN NETWORK DEVICES 有权
    网络设备中的队列

    公开(公告)号：US20110113197A1

    公开(公告)日：2011-05-12

    申请号：US12941802

    申请日：2010-11-08

    Applicant: Gilbert Wolrich ,  Mark B. Rosenbluth ,  Debra Bernstein

    Inventor： Gilbert Wolrich ,  Mark B. Rosenbluth ,  Debra Bernstein

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  H04L49/90 ,  H04L49/901

    Abstract: A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from the memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation.

    Abstract translation: 包括指向队列中的第一个元素的头指针和指向队列中最后一个元素的尾指针的队列描述符存储在内存中。 响应于执行相对于队列的入队或出队操作的命令，从存储器获取仅缓存头指针或尾指针中的一个，并从由队列描述符修改的队列描述符的高速缓存部分返回到存储器 的操作。

    Thread signaling in multi-threaded processor
    7.
    发明授权
    Thread signaling in multi-threaded processor 失效
    线程信令在多线程处理器中

    公开(公告)号：US07111296B2

    公开(公告)日：2006-09-19

    申请号：US10615280

    申请日：2003-07-08

    Applicant: Gilbert Wolrich ,  Debra Bernstein ,  Donald Hooper ,  Matthew J. Adiletta ,  William Wheeler

    Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Donald Hooper ,  Matthew J. Adiletta ,  William Wheeler

    IPC: G06F9/46

    CPC classification number: G06F9/4843 ,  G06F9/3851

    Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.

    Abstract translation: 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。 还描述了用于分组处理的程序线程通信方案。

    Enqueueing entries in a packet queue referencing packets
    9.
    发明申请
    Enqueueing entries in a packet queue referencing packets 有权
    引用数据包的数据包队列中的入队条目

    公开(公告)号：US20060069869A1

    公开(公告)日：2006-03-30

    申请号：US10936917

    申请日：2004-09-08

    Applicant: Sridhar Lakshmanamurthy ,  Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

    Inventor： Sridhar Lakshmanamurthy ,  Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

    IPC: G06F12/14

    CPC classification number: G06F12/0804 ,  G06F12/0875

    Abstract: Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area referencing the added packet. A pointer is read referencing one end of the packet queue from a queue descriptor in the second memory area into a third memory area in one read operation. The pointer is updated in the third memory area to point to the added entry in the packet queue and the updated pointer in the third memory area is written to the queue descriptor in the second memory area in one write operation

    Abstract translation: 提供了一种方法，系统，网络处理器，网络设备和用于引入分组的分组队列中的入口的入口制品。 当向第一存储器区域添加分组时，将条目写入参考所添加的分组的第二存储器区域中的分组队列。 在一次读取操作中，将指针从第二存储器区域中的队列描述符引用到分组队列的一端到第三存储器区域中。 指针在第三存储器区域中更新以指向分组队列中的添加的条目，并且在一个写入操作中将第三存储器区域中的更新的指针写入第二存储器区域中的队列描述符

    Memory access control
    10.
    发明授权
    Memory access control 失效
    内存访问控制

    公开(公告)号：US06973550B2

    公开(公告)日：2005-12-06

    申请号：US10264092

    申请日：2002-10-02

    Applicant: Mark B. Rosenbluth ,  Gilbert M. Wolrich ,  Debra Bernstein ,  Richard Guerin

    Inventor： Mark B. Rosenbluth ,  Gilbert M. Wolrich ,  Debra Bernstein ,  Richard Guerin

    IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

    CPC classification number: G06F13/1642

    Abstract: In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.

    Abstract translation: 通常，在一个方面，本公开描述了存储与不同的，相应的排队的写入命令相关联的一个或多个存储器桶的标识，并且基于所存储的标识，确定与读取命令相关联的至少一个桶是否包括在 与至少一个排队的写入命令相关联的一个或多个存储桶。

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