Invention Grant
- Patent Title: Delay-locked loop circuit of a semiconductor device and method of controlling the same
- Patent Title (中): 半导体器件的延迟锁定环路电路及其控制方法
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Application No.: US11623925Application Date: 2007-01-17
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Publication No.: US07477715B2Publication Date: 2009-01-13
- Inventor: Young-Yong Byun , Dong-Jin Lee , Hi-Choon Lee
- Applicant: Young-Yong Byun , Dong-Jin Lee , Hi-Choon Lee
- Applicant Address: KR Suwon-Si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-Si
- Agency: F. Chau & Associates, LLC
- Priority: KR10-2006-0009703 20060201
- Main IPC: H03D3/24
- IPC: H03D3/24

Abstract:
A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.
Public/Granted literature
- US20070176657A1 DELAY-LOCKED LOOP CIRCUIT OF A SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME Public/Granted day:2007-08-02
Information query
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