Invention Grant
- Patent Title: Method and apparatus for testing logic circuit designs
- Patent Title (中): 用于测试逻辑电路设计的方法和装置
-
Application No.: US11538245Application Date: 2006-10-03
-
Publication No.: US07484151B2Publication Date: 2009-01-27
- Inventor: Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
- Applicant: Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
- Applicant Address: US NJ Princeton
- Assignee: NEC Laboratories America, Inc.
- Current Assignee: NEC Laboratories America, Inc.
- Current Assignee Address: US NJ Princeton
- Agent Joseph J. Kolodka; James Bitetto
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.
Public/Granted literature
- US20070113129A1 Method and Apparatus for Testing Logic Circuit Designs Public/Granted day:2007-05-17
Information query