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    Method and apparatus for testing logic circuit designs
    1.
    发明授权
    Method and apparatus for testing logic circuit designs 失效
    用于测试逻辑电路设计的方法和装置

    公开(公告)号：US07484151B2

    公开(公告)日：2009-01-27

    申请号：US11538245

    申请日：2006-10-03

    Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    IPC: G01R31/28

    CPC classification number: G01R31/31921

    Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

    Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

    Method and Apparatus for Testing Logic Circuit Designs
    2.
    发明申请
    Method and Apparatus for Testing Logic Circuit Designs 失效
    逻辑电路设计测试方法与装置

    公开(公告)号：US20070113129A1

    公开(公告)日：2007-05-17

    申请号：US11538245

    申请日：2006-10-03

    Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat Chakradhar

    Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat Chakradhar

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: G01R31/31921

    Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

    Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

    Test Output Compaction with Improved Blocking of Unknown Values
    3.
    发明申请
    Test Output Compaction with Improved Blocking of Unknown Values 失效
    测试输出压缩，改进阻塞未知值

    公开(公告)号：US20060236186A1

    公开(公告)日：2006-10-19

    申请号：US11276771

    申请日：2006-03-14

    Applicant: Seongmoon Wang ,  Kedarnath Balakrishnan ,  Srimat Chakradhar

    Inventor： Seongmoon Wang ,  Kedarnath Balakrishnan ,  Srimat Chakradhar

    IPC: G01R31/28 ,  G06F11/00

    CPC classification number: G01R31/318335 ,  G01R31/3181

    Abstract: A test output compaction arrangement and a method of generating control patterns for unknown blocking is herein disclosed. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to balance the number of specified bits in the control patterns across test patterns.

    Abstract translation: 本文公开了测试输出压缩装置和产生未知阻塞的控制模式的方法。 当使用线性反馈移位寄存器（LFSR）重新进给确定控制数据量和LFSR大小时，控制模式中的指定位优选地以使得跨越测试模式平衡控制模式中的指定位的数目的方式来组织。

    METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS
    4.
    发明申请
    METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS 失效
    用于测试逻辑电路设计的方法和装置

    公开(公告)号：US20090119556A1

    公开(公告)日：2009-05-07

    申请号：US12265330

    申请日：2008-11-05

    Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    IPC: G01R31/3177 ,  G06F11/25

    CPC classification number: G01R31/31921

    Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

    Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

    Method for generating, from a test cube set, a generator configured to generate a test pattern
    8.
    发明授权
    Method for generating, from a test cube set, a generator configured to generate a test pattern 失效
    从测试立方体集合生成被配置为生成测试图案的生成器的方法

    公开(公告)号：US07610540B2

    公开(公告)日：2009-10-27

    申请号：US12265300

    申请日：2008-11-05

    Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    IPC: G06F11/00 ,  G06G7/58

    CPC classification number: G01R31/31921

    Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.

    Abstract translation: 公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。 测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。 解压缩器被配置为从种子和扫描输入的位置生成测试图案。 解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

    Register Transfer Level (RTL) Test Point Insertion Method to Reduce Delay Test Volume
    9.
    发明申请
    Register Transfer Level (RTL) Test Point Insertion Method to Reduce Delay Test Volume 审中-公开
    寄存器传输级别（RTL）测试点插入方法来减少延迟测试卷

    公开(公告)号：US20080092093A1

    公开(公告)日：2008-04-17

    申请号：US11858216

    申请日：2007-09-20

    Applicant: Kedarnath Balakrishnan ,  Lei Fang

    Inventor： Kedarnath Balakrishnan ,  Lei Fang

    IPC: G01R31/3185

    CPC classification number: G01R31/318547 ,  G01R31/318328

    Abstract: A method includes inserting test points into a circuit for reducing the number of specified bits required for transition fault testing of the circuit by reducing the dependency of a second time-frame pattern of the circuit on a first time-frame pattern of the circuit. Preferably, inserting the test points includes controlling directly scan flip-flops of the circuit in the second time-frame requiring a number of scan flip-flops to be specified in the first time-frame for reducing the number of specified bits to detect transition faults.

    Abstract translation: 一种方法包括将测试点插入到电路中，以通过减少电路的第二时间帧图案对电路的第一时间帧图案的依赖性来减少电路的转换故障测试所需的指定位数。 优选地，插入测试点包括在第二时间帧中直接扫描电路的触发器，需要在第一时间帧中指定多个扫描触发器，以减少指定位数来检测转变故障 。

    Method and Apparatus for Testing an Integrated Circuit
    10.
    发明申请
    Method and Apparatus for Testing an Integrated Circuit 审中-公开
    用于测试集成电路的方法和装置

    公开(公告)号：US20070266283A1

    公开(公告)日：2007-11-15

    申请号：US11692367

    申请日：2007-03-28

    Applicant: Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    Inventor： Kedarnath Balakrishnan ,  Seongmoon Wang ,  Wenlong Wei ,  Srimat T. Chakradhar

    IPC: G01R31/28

    CPC classification number: G01R31/318547

    Abstract: Disclosed is an apparatus and method for testing an IC having a plurality of scan chains. A test input is transmitted over a tester channel to at least one scan chain during a time interval. Specifically, a memory element stores a first test input transmitted during a first time interval and a combinational circuit connected to the memory element and scan chain transmits to the scan chain one of a) the first test input and b) a second test input transmitted over the tester channel during a second time interval occurring after the first time interval.

    Abstract translation: 公开了一种用于测试具有多个扫描链的IC的装置和方法。 在一段时间间隔内，测试输入通过测试仪通道发送到至少一个扫描链。 具体地，存储元件存储在第一时间间隔期间发送的第一测试输入和连接到存储元件的组合电路，扫描链将扫描链传送到扫描链a）第一测试输入中的一个，以及b）传输的第二测试输入 在第一时间间隔之后的第二时间间隔期间发生测试仪通道。

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