Invention Grant
- Patent Title: Structure for joining a semiconductor package to a substrate using a solder column
- Patent Title (中): 使用焊料柱将半导体封装与基板接合的结构
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Application No.: US11330773Application Date: 2006-01-11
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Publication No.: US07485959B2Publication Date: 2009-02-03
- Inventor: Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
- Applicant: Cheol-Joon Yoo , Jin-Ho Kim , Hee-Jin Park , Tae-Sung Yoon , Chan-Suk Lee
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR10-2005-0003751 20050114
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/44
Abstract:
A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.
Public/Granted literature
- US20060157848A1 Structure and method for joining a semiconductor package to a substrate using solder column Public/Granted day:2006-07-20
Information query
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