公开(公告)号：US20060157848A1

公开(公告)日：2006-07-20

申请号：US11330773

申请日：2006-01-11

申请人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

发明人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one embodiment, a semiconductor package and a package mounting substrate are joined using a conductive material column such as a solder column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. By forming the insulating protective openings with sufficient depth, each protects the solder column against stress faults and thereby forms more reliable electrical connections and supports high-density electrical connections between the semiconductor package and the package mounting substrate.

摘要翻译： 在一个实施例中，使用诸如焊料柱的导电材料柱将半导体封装和封装安装基板接合。 半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。 焊料柱位于绝缘保护开口内，以电连接布线层。 通过形成具有足够深度的绝缘保护开口，每个保护焊料柱免受应力故障，从而形成更可靠的电连接并且支持半导体封装和封装安装基板之间的高密度电连接。

公开(公告)号：US07485959B2

公开(公告)日：2009-02-03

申请号：US11330773

申请日：2006-01-11

申请人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

发明人： Cheol-Joon Yoo ,  Jin-Ho Kim ,  Hee-Jin Park ,  Tae-Sung Yoon ,  Chan-Suk Lee

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.

摘要翻译： 半导体封装和封装安装基板可以使用导电材料柱接合。 半导体封装和封装安装衬底中的每一个包括暴露其中的布线层的绝缘保护开口。 焊料柱位于绝缘保护开口内，以电连接布线层。 绝缘保护开口保护焊料柱免受应力故障的影响，形成可靠的电连接并支持半导体封装和封装安装基板之间的高密度电连接。

公开(公告)号：US20080111284A1

公开(公告)日：2008-05-15

申请号：US11985146

申请日：2007-11-14

申请人： Cheol-Joon Yoo ,  Tae-Sung Yoon

发明人： Cheol-Joon Yoo ,  Tae-Sung Yoon

IPC分类号： B29C43/18

CPC分类号： B29C43/183 ,  B29C33/68 ,  B29C43/146 ,  B29C2043/3411 ,  B29C2043/3605 ,  B29K2105/251 ,  B29L2031/772 ,  H05K3/0014

摘要： In a method of molding a substrate, a molding structure including a release film and flat plate-shaped epoxy molding compound (EMC) is placed on an upper face of a lower die. The substrate is held by a lower face of an upper die facing the lower die. The molding structure and the substrate are compressed using the lower die and the upper die to form a preliminarily molded substrate. The lower die is then downwardly moved from the upper die to form a molded substrate.

摘要翻译： 在成型基板的方法中，将包含脱模膜和平板状环氧树脂模塑料（EMC）的模制结构放置在下模的上表面上。 基板由面向下模的上模的下表面保持。 使用下模和上模压缩成形结构和基板，以形成预成型基板。 然后将下模从上模向下移动以形成模制基板。

公开(公告)号：US20050269715A1

公开(公告)日：2005-12-08

申请号：US11029566

申请日：2005-01-06

申请人： Cheol-Joon Yoo

发明人： Cheol-Joon Yoo

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L23/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC分类号： H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus, method and mold for manufacturing a semiconductor package are provided. The semiconductor package may include at least a semiconductor chip positioned on a substrate, a bonding wire for electrically connecting the semiconductor chip to the substrate, an encapsulant for enclosing the semiconductor chip and sides of the substrate, and a conductor connector attached to a lower surface of the substrate.

摘要翻译： 提供一种用于制造半导体封装的设备，方法和模具。 半导体封装可以包括位于基板上的至少一个半导体芯片，用于将半导体芯片电连接到基板的接合线，用于封装半导体芯片的密封剂和衬底的侧面，以及连接到下表面的导体连接器 的基底。

公开(公告)号：US20080042253A1

公开(公告)日：2008-02-21

申请号：US11976253

申请日：2007-10-23

申请人： Cheol-Joon Yoo

发明人： Cheol-Joon Yoo

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225

摘要： A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.

摘要翻译： 堆叠的BGA封装和用于制造堆叠的BGA封装的方法，其具有减小的单元封装的尺寸和/或高度，这也可以减小电连接长度。 堆叠的BGA封装可以包括具有至少一个半导体芯片的基底BGA封装和堆叠在基底BGA封装上的多个BGA封装。 多个焊球可以电连接基底BGA封装和多个BGA封装，然后可以被密封以减少损坏的可能性。

公开(公告)号：US07298033B2

公开(公告)日：2007-11-20

申请号：US10834186

申请日：2004-04-29

申请人： Cheol-Joon Yoo

发明人： Cheol-Joon Yoo

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225

摘要： A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.

摘要翻译： 堆叠的BGA封装和用于制造堆叠的BGA封装的方法，其具有减小的单元封装的尺寸和/或高度，这也可以减小电连接长度。 堆叠的BGA封装可以包括具有至少一个半导体芯片的基底BGA封装和堆叠在基底BGA封装上的多个BGA封装。 多个焊球可以电连接基底BGA封装和多个BGA封装，然后可以被密封以减少损坏的可能性。

公开(公告)号：US06869264B2

公开(公告)日：2005-03-22

申请号：US10435202

申请日：2003-05-12

申请人： Cheol-Joon Yoo

发明人： Cheol-Joon Yoo

IPC分类号： H01L21/50 ,  H01L21/00 ,  H01L21/68 ,  B65B21/02

CPC分类号： H01L21/6835 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68322 ,  H01L2221/68327

摘要： A method and apparatus for picking up a semiconductor chip, a method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape are provided. Air may be blown through air holes in a dicing tape to at least partially separate the semiconductor chip from the dicing tape and/or create a space between the semiconductor chip to weaken the adhesion of the dicing tape to the semiconductor chip. The semiconductor chip may then be picked up by a removal member and completely removed from the dicing tape. Semiconductor chips that are not to be removed may be vacuum-suctioned to the dicing tape. UV radiation or heat may be applied to weaken the adhesion of the dicing tape. The semiconductor chip may be detected by an optical detector. Removing the semiconductor chips by air reduces stress and damage to the semiconductor chips.

公开(公告)号：US07939924B2

公开(公告)日：2011-05-10

申请号：US11976253

申请日：2007-10-23

申请人： Cheol-Joon Yoo

发明人： Cheol-Joon Yoo

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225

摘要： A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.

摘要翻译： 堆叠的BGA封装和用于制造堆叠的BGA封装的方法，其具有减小的单元封装的尺寸和/或高度，这也可以减小电连接长度。 堆叠的BGA封装可以包括具有至少一个半导体芯片的基底BGA封装和堆叠在基底BGA封装上的多个BGA封装。 多个焊球可以电连接基底BGA封装和多个BGA封装，然后可以被密封以减少损坏的可能性。

公开(公告)号：US20090166061A1

公开(公告)日：2009-07-02

申请号：US12318372

申请日：2008-12-29

申请人： Cheol-Joon Yoo ,  Tae-Sung Park

发明人： Cheol-Joon Yoo ,  Tae-Sung Park

IPC分类号： H05K1/00 ,  H05K3/00

CPC分类号： H05K3/0097 ,  H05K3/0052 ,  H05K2203/1554 ,  Y10T29/49124

摘要： A PCB strip, a PCB strip assembly device, and methods of fabricating a PCB strip and using a PCB strip assembly device are provided. According to example embodiments, a PCB strip may include a PCB main body including a working area based on a process execution unit, wherein the working area may be divided into a first working area and a second working area and a plurality of units on the working area arrayed with a given interval in at least a width direction of the PCB main body, wherein the plurality of units may be arrayed on the first working area and the second working area and units on the first working area may be symmetric to units on the second working area with respect to a point of symmetry at a center of width of the working area.

摘要翻译： 提供了PCB板条，PCB板组装装置以及PCB板的制造方法和PCB板组装装置。 根据示例性实施例，PCB板可以包括PCB主体，其包括基于处理执行单元的工作区域，其中工作区域可分为第一工作区域和第二工作区域以及工作区域上的多个单元 在PCB主体的至少宽度方向上以给定的间隔排列的区域，其中多个单元可以排列在第一工作区域和第二工作区域上，并且第一工作区域上的单元可以与第一工作区域上的单元对称 相对于工作区域的宽度中心处的对称点的第二工作区域。

公开(公告)号：US07284941B2

公开(公告)日：2007-10-23

申请号：US10981443

申请日：2004-11-05

申请人： Cheol-Joon Yoo

发明人： Cheol-Joon Yoo

IPC分类号： B65B21/02

CPC分类号： H01L21/6835 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68322 ,  H01L2221/68327

摘要： A method and apparatus for picking up a semiconductor chip, a method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape are provided. Air may be blown through air holes in a dicing tape to at least partially separate the semiconductor chip from the dicing tape and/or create a space between the semiconductor chip to weaken the adhesion of the dicing tape to the semiconductor chip. The semiconductor chip may then be picked up by a removal member and completely removed from the dicing tape. Semiconductor chips that are not to be removed may be vacuum-suctioned to the dicing tape. UV radiation or heat may be applied to weaken the adhesion of the dicing tape. The semiconductor chip may be detected by an optical detector. Removing the semiconductor chips by air reduces stress and damage to the semiconductor chips.

摘要翻译： 提供一种用于拾取半导体芯片的方法和装置，用于从切割带去除半导体芯片的方法和装置以及形成穿孔切割带的方法。 空气可以通过切割带中的空气孔吹入，以将半导体芯片与切割带至少部分分离和/或在半导体芯片之间产生空间，以削弱切割带对半导体芯片的粘附。 半导体芯片然后可以由去除构件拾取并从切割带完全移除。 不要去除的半导体芯片可以被真空吸附到切割带上。 可以施加UV辐射或热量以削弱切割胶带的粘附。 半导体芯片可以由光学检测器检测。 用空气去除半导体芯片减少对半导体芯片的压力和损坏。