Power-gated circuitry is put in a “sleep mode” that selectively gates both the power supply rails for static power control and the clock distribution for dynamic power control. A time interval M is established following a wake-up signal that includes the time to power-up, perform a computation, and return a result to the following circuitry. Likewise, a time interval N is established that indicates how long to wait after a result is returned before the power-gated circuitry is returned to the sleep mode to assure a desired performance. When a power-gated circuit is going to be needed for a future computation, it is issued a wake-up signal and a predetermined estimated time K for receipt of a next wake-up signal. A decision is made by analyzing the times M, N, and K as to when to return a power-gated circuit to the sleep mode following activation by a wake-up signal.