公开(公告)号：US07487374B2

公开(公告)日：2009-02-03

申请号：US11034556

申请日：2005-01-13

申请人： Ying Liu ,  Jente B. Kuang ,  Hung C. Ngo

发明人： Ying Liu ,  Jente B. Kuang ,  Hung C. Ngo

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171

摘要： Power-gated circuitry is put in a “sleep mode” that selectively gates both the power supply rails for static power control and the clock distribution for dynamic power control. A time interval M is established following a wake-up signal that includes the time to power-up, perform a computation, and return a result to the following circuitry. Likewise, a time interval N is established that indicates how long to wait after a result is returned before the power-gated circuitry is returned to the sleep mode to assure a desired performance. When a power-gated circuit is going to be needed for a future computation, it is issued a wake-up signal and a predetermined estimated time K for receipt of a next wake-up signal. A decision is made by analyzing the times M, N, and K as to when to return a power-gated circuit to the sleep mode following activation by a wake-up signal.

摘要翻译： 电源门控电路被置于“休眠模式”中，选择性地将电源轨两端门控，用于静态功率控制和用于动态功率控制的时钟分配。 在包括上电时间，执行计算并将结果返回到以下电路的唤醒信号之后建立时间间隔M. 类似地，建立时间间隔N，其指示在电源门控电路返回到睡眠模式之前在返回结果之后等待多久以确保期望的性能。 当将来需要一个电源门控电路时，它将发出一个唤醒信号和一个预定的估计时间K，用于接收下一个唤醒信号。 通过分析在唤醒信号激活之后何时将电源门控电路返回到休眠模式的时间M，N和K进行判断。

公开(公告)号：US07719315B2

公开(公告)日：2010-05-18

申请号：US11554666

申请日：2006-10-31

申请人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

发明人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

IPC分类号： H03K19/00

CPC分类号： G06F1/10 ,  G01R31/318552

摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.

摘要翻译： 可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。 时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。 延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。 全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。 扫描时钟前馈电路接收本地时钟并产生扫描时钟。 数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。 以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

公开(公告)号：US20080201672A1

公开(公告)日：2008-08-21

申请号：US11762257

申请日：2007-06-13

申请人： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

发明人： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC分类号： G06F17/50

CPC分类号： G01R31/31725

摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

摘要翻译： 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US20080100360A1

公开(公告)日：2008-05-01

申请号：US11553014

申请日：2006-10-26

申请人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

发明人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

IPC分类号： H03K3/017

CPC分类号： H03K3/017 ,  G01R31/31727 ,  G06F1/10 ,  H03K3/0315 ,  H03K5/133 ,  H03K5/135 ,  H03K5/156

摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.

摘要翻译： 在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。 输出驱动器输出脉宽调整信号。 脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。 第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。 脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。 可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

公开(公告)号：US06975134B2

公开(公告)日：2005-12-13

申请号：US10821048

申请日：2004-04-08

申请人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： H03K17/16 ,  H03K19/00 ,  H03K19/003 ,  H03K19/017

CPC分类号： H03K19/00361 ,  H03K19/0016 ,  H03K19/01721

摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

摘要翻译： 具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。 第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。 第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。 每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。 第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。 当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。 缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。

公开(公告)号：US20120212997A1

公开(公告)日：2012-08-23

申请号：US13459932

申请日：2012-04-30

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US20080155362A1

公开(公告)日：2008-06-26

申请号：US11552158

申请日：2006-10-24

申请人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Leland Chang ,  Jente B. Kuang ,  Robert K. Montoye ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： G11C29/00

CPC分类号： G11C8/16 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50012

摘要： A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.

摘要翻译： 用于表征生产静态随机存取存储器（SRAM）阵列的测试结构。 测试结构包括具有串联连接的多个存储单元列的表征电路，以形成环形结构。 表征电路在与生产SRAM阵列相同并且靠近生产SRAM阵列的晶片衬底上制造。 表征电路优选地包括具有与生产SRAM阵列内的存储器单元的电路拓扑基本相同的电路拓扑的SRAM单元。 在一个实施例中，测试结构用于表征多端口存储器阵列，并且包括串联连接的多个存储单元列，以形成环形振荡器表征电路。 表征电路中的每个单元列包括多个具有锁存节点和多个数据路径接入节点的SRAM单元。 选择控制电路选择性地启用表征电路内的SRAM单元的多个数据路径接入节点。

公开(公告)号：US20080101522A1

公开(公告)日：2008-05-01

申请号：US11554666

申请日：2006-10-31

申请人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

发明人： Hung C. Ngo ,  Jente B. Kuang ,  James D. Warnock ,  Dieter F. Wendel

IPC分类号： H04L7/00

CPC分类号： G06F1/10 ,  G01R31/318552

摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.

摘要翻译： 可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。 时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。 延迟控制信号反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。 全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。 扫描时钟前馈电路接收本地时钟并产生扫描时钟。 数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。 以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

公开(公告)号：US07276932B2

公开(公告)日：2007-10-02

申请号：US10926597

申请日：2004-08-26

申请人： Jente B. Kuang ,  Jethro C. Law ,  Hung C. Ngo ,  Kevin J. Nowka

发明人： Jente B. Kuang ,  Jethro C. Law ,  Hung C. Ngo ,  Kevin J. Nowka

IPC分类号： H03K19/23

CPC分类号： H03K19/0016

摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.

摘要翻译： 虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。 每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。 在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。 控制信号在单元边界被锁存或响应于时钟信号锁存。

公开(公告)号：US06980018B2

公开(公告)日：2005-12-27

申请号：US10835501

申请日：2004-04-29

申请人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

发明人： Hung C. Ngo ,  Jente B. Kuang ,  Kevin J. Nowka

IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/094

CPC分类号： H03K19/01721 ,  H03K19/00361

摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.

摘要翻译： 具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。 第一个逻辑路径由小型设备组成，并配置为提供缓冲区的逻辑功能，无需驱动大负载。 第二和第三逻辑路径具有直到最后一个反相级的第一逻辑路径的逻辑功能。 每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。 第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。 当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。 缓冲器可以是逆变器，非逆变器，或提供多输入逻辑功能。