发明授权
US07498653B2 Semiconductor structure for isolating integrated circuits of various operating voltages
有权
用于隔离各种工作电压的集成电路的半导体结构
- 专利标题: Semiconductor structure for isolating integrated circuits of various operating voltages
- 专利标题(中): 用于隔离各种工作电压的集成电路的半导体结构
-
申请号: US11273228申请日: 2005-11-12
-
公开(公告)号: US07498653B2公开(公告)日: 2009-03-03
- 发明人: Chia-Wei Liu , Jun Xiu Liu , Chi-Hsuen Chang , Tzu-Chiang Sung , Chung-I Chen , Rann-Shyan Yeh
- 申请人: Chia-Wei Liu , Jun Xiu Liu , Chi-Hsuen Chang , Tzu-Chiang Sung , Chung-I Chen , Rann-Shyan Yeh
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: K & L Gates LLP
- 主分类号: H01L29/00
- IPC分类号: H01L29/00
摘要:
A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.
公开/授权文献
信息查询
IPC分类: