Invention Grant
- Patent Title: Tri-gate devices and methods of fabrication
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Application No.: US10703316Application Date: 2003-11-07
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Publication No.: US07504678B2Publication Date: 2009-03-17
- Inventor: Robert S. Chau , Brian S. Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta
- Applicant: Robert S. Chau , Brian S. Doyle , Jack Kavalieros , Douglas Barlage , Suman Datta
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Rahul D. Engineer
- Main IPC: H01L29/80
- IPC: H01L29/80 ; H01L31/112
Abstract:
The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
Public/Granted literature
- US20040094807A1 Tri-gate devices and methods of fabrication Public/Granted day:2004-05-20
Information query
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