Invention Grant
US07510946B2 Method for filling of nanoscale holes and trenches and for planarizing of a wafer surface
有权
用于填充纳米级孔和沟槽以及用于平坦化晶片表面的方法
- Patent Title: Method for filling of nanoscale holes and trenches and for planarizing of a wafer surface
- Patent Title (中): 用于填充纳米级孔和沟槽以及用于平坦化晶片表面的方法
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Application No.: US11533323Application Date: 2006-09-19
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Publication No.: US07510946B2Publication Date: 2009-03-31
- Inventor: Stephen Y. Chou , Bo Cui , Christopher F. Keimel
- Applicant: Stephen Y. Chou , Bo Cui , Christopher F. Keimel
- Applicant Address: US NJ Princeton
- Assignee: Princeton University
- Current Assignee: Princeton University
- Current Assignee Address: US NJ Princeton
- Agency: Polster, Lieder, Woodruff & Lucchesi, LC
- Main IPC: H01L21/3105
- IPC: H01L21/3105

Abstract:
A processing method for use in the fabrication of fabrication of nanoscale electronic, optical, magnetic, biological, and fluidic devices and structures, for filling nanoscale holes and trenches, for planarizing a wafer surface, or for achieving both filling and planarizing of a wafer surface simultaneously. The method has the initial step of depositing a layer of a meltable material on a wafer surface. The material is then pressed using a transparent mold while shining a light pulse through the transparent mold to melt the deposited layer of meltable material. A flow of the molten layer material fills the holes and trenches, and conforms to surface features on the transparent mold. The transparent mold is subsequently removed.
Public/Granted literature
- US20070082457A1 Method For Filling Of Nanoscale Holes And Trenches And For Planarizing Of A Wafer Surface Public/Granted day:2007-04-12
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