发明授权
- 专利标题： Protection of three dimensional transistor structures during gate stack etch
- 专利标题（中）： 在栅堆叠蚀刻期间保护三维晶体管结构
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申请号： US11452883申请日： 2006-06-13
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公开(公告)号： US07521775B2公开(公告)日： 2009-04-21
- 发明人: Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
- 申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Kenneth A. Nelson
- 主分类号： H01L29/06
- IPC分类号： H01L29/06
摘要：
Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.