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发明授权
US07521775B2 Protection of three dimensional transistor structures during gate stack etch 有权
在栅堆叠蚀刻期间保护三维晶体管结构

Protection of three dimensional transistor structures during gate stack etch
摘要：
Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要（中）：

本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅​​片由其顶表面上的硬掩模层保护。 在一个实施例中，硬掩模层包括氧化物。

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