Invention Grant
- Patent Title: Memory device and semiconductor integrated circuit
- Patent Title (中): 存储器件和半导体集成电路
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Application No.: US11883653Application Date: 2006-04-21
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Publication No.: US07525832B2Publication Date: 2009-04-28
- Inventor: Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Hiroshi Seki
- Applicant: Shunsaku Muraoka , Koichi Osano , Satoru Mitani , Hiroshi Seki
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-125686 20050422; JP2005-308627 20051024
- International Application: PCT/JP2006/308433 WO 20060421
- International Announcement: WO2006/115208 WO 20061102
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
First electrode layer includes a plurality of first electrode lines (W1, W2) extending parallel to each other. State-variable layer lying on the first electrode layer includes a plurality of state-variable portions (60-11, 60-12, 60-21, 60-22) which exhibits a diode characteristic and a variable-resistance characteristic. Second electrode layer lying on the state-variable layer includes a plurality of second electrode lines (B1, B2) extending parallel to each other. The plurality of first electrode lines and the plurality of second electrode lines are crossing each other when seen in a layer-stacking direction with the state-variable layer interposed therebetween. State-variable portion (60-11) is provided at an intersection of the first electrode line (W1) and the second electrode line (B1) between the first electrode line and the second electrode line.
Public/Granted literature
- US20080212359A1 Memory Device and Semiconductor Integrated Circuit Public/Granted day:2008-09-04
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