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US07528619B2 0th droop detector architecture and implementation 有权
第0个下垂检测器架构和实现

0th droop detector architecture and implementation
摘要:
A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.
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