Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Invention Grant

US07531437B2 Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material 有权

Title translation: 使用牺牲栅电极材料和牺牲栅介质材料形成金属栅电极的方法

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Patent Title: Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
Patent Title (中): 使用牺牲栅电极材料和牺牲栅介质材料形成金属栅电极的方法
Application No.: US11360269

Application Date: 2006-02-22
Publication No.: US07531437B2

Publication Date: 2009-05-12
Inventor: Justin K. Brask , Brian S. Doyle , Jack Kavalieros , Mark Doczy , Uday Shah , Robert S. Chau
Applicant: Justin K. Brask , Brian S. Doyle , Jack Kavalieros , Mark Doczy , Uday Shah , Robert S. Chau
Applicant Address: US CA Santa Clara
Assignee: Intel Corporation
Current Assignee: Intel Corporation
Current Assignee Address: US CA Santa Clara
Agency: Blakely, Sokoloff, Taylor & Zafman LLP
Main IPC: H01L21/3205
IPC: H01L21/3205

Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Abstract:

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract(Chinese):

要求保护半导体器件，该半导体器件具有形成在绝缘衬底上的具有顶表面和第一和第二横向相对侧壁的半导体本体。在半导体本体的顶表面和半导体本体的第一和第二横向相对的侧壁上形成栅极电介质。然后在半导体主体的顶表面上的栅电介质上形成栅电极，并且与半导体本体的第一和第二横向相对的侧壁上的栅电介质相邻。栅电极包括直接与栅介电层相邻形成的金属膜。然后在栅电极的相对侧上的半导体本体中形成一对源区和漏区。

Public/Granted literature

US20060138552A1 Nonplanar transistors with metal gate electrodes Public/Granted day:2006-06-29

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3205	......非绝缘层的沉积，例如绝缘层上的导电层或电阻层；这些层的后处理（电极的制造入H01L21/28）