发明授权
- 专利标题: Delay locked loop circuit and method
- 专利标题(中): 延时锁相环电路及方法
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申请号: US11906872申请日: 2007-10-04
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公开(公告)号: US07532050B2公开(公告)日: 2009-05-12
- 发明人: Dieter Haerle , Tony Mai , Peter Vlasenko
- 申请人: Dieter Haerle , Tony Mai , Peter Vlasenko
- 申请人地址: CA Kanata, Ontario
- 专利权人: MOSAID Technologies, Inc.
- 当前专利权人: MOSAID Technologies, Inc.
- 当前专利权人地址: CA Kanata, Ontario
- 代理机构: Hamilton, Brook, Smith & Reynolds, P.C.
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
公开/授权文献
- US20080030247A1 Delay locked loop circuit and method 公开/授权日:2008-02-07
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