公开(公告)号：US20130234787A1

公开(公告)日：2013-09-12

申请号：US13873503

申请日：2013-04-30

申请人： MOSAID TECHNOLOGIES, INC.

发明人： Peter Vlasenko ,  Huy Tuong Mai

IPC分类号： G05F3/02

CPC分类号： H02M3/07 ,  G05F1/625 ,  G05F3/02 ,  H02M1/34 ,  H02M3/073 ,  H03K5/086 ,  H03L7/0895

摘要： A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

公开(公告)号：US08295185B2

公开(公告)日：2012-10-23

申请号：US11841463

申请日：2007-08-20

申请人： Yehuda Binder

发明人： Yehuda Binder

IPC分类号： G01R31/08

CPC分类号： H04L12/44 ,  H04L12/2803 ,  H04L12/2818 ,  H04L12/2827 ,  H04L29/12839 ,  H04L41/0677 ,  H04L61/6022 ,  H04L2012/2843 ,  H04L2012/2845

摘要： An addressable outlet for use as part of local area network based on wiring installed in a building, such as telephone, electrical, cable television, dedicated wiring, and the like. The use of such wiring for data communications networks in addition to the wiring's primary usage creates a need for ways of determining the condition of the network and monitoring this information remotely. Network condition includes such factors as continuity of wiring, connector status, connected devices, topology, signal delays, latencies, and routing patterns. Providing basic processing and addressing capabilities within the outlet permits messaging to and from specific individual outlets, thereby allowing inquiries and reports of the condition of the immediate environment of each outlet. In addition, outlets can be configured with sensors to report on voltage, temperature, and other measurable quantities.

摘要翻译： 基于安装在诸如电话，电气，有线电视，专用布线等的建筑物中的布线用作局域网的一部分的可寻址插座。 除了布线的主要用途之外，对数据通信网络使用这种布线还需要确定网络状况并远程监控该信息的方法。 网络状况包括布线连续性，连接器状态，连接设备，拓扑，信号延迟，延迟和路由模式等因素。 在插座内提供基本的处理和寻址功能，可以与特定的个人插座进行通信，从而允许查询和报告每个插座的即时环境状况。 此外，插座可以配置传感器来报告电压，温度和其他可测量的数量。

公开(公告)号：US20090201058A2

公开(公告)日：2009-08-13

申请号：US12214053

申请日：2008-06-16

申请人： Dieter Haerle

发明人： Dieter Haerle

IPC分类号： H03L7/06

CPC分类号： H03L7/0895 ,  H03L7/0812

摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operations amplifier also mitigates the effects of low power supply voltage.

摘要翻译： 用于锁相环/延迟锁定环的电荷泵通过使用运算放大器将静态相位误差最小化。 运算放大器还可以减轻低电源电压的影响。

公开(公告)号：US07535749B2

公开(公告)日：2009-05-19

申请号：US11396306

申请日：2006-03-30

申请人： Valerie L. Lines

发明人： Valerie L. Lines

IPC分类号： G11C11/24

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.

摘要翻译： 准确地将字线（传输晶体管栅极）驱动电压控制到电压的电路，该电压被控制并且不显着大于驱动字线所需的电压。 该电路消除了双引导电路的需要，并确保没有电压超过完全打开存储单元存取晶体管所需的电压。 避免超过降低可靠性的电压，并获得精确的驱动电压。 DRAM包括字线，具有连接到字线的使能输入的存储器单元，栅极接收字线以第一逻辑电平Vss和Vdd选择信号，以及用于提供电平Vss和Vdd的选择信号，高电压源Vpp 其电压高于Vdd，用于将电平Vss和Vdd的选择信号转换为电平Vss和Vpp并用于将其直接应用于字线的电路，从而实现上述Vdd电压电平字线而不使用双引导 - 电路。

公开(公告)号：US20080252342A1

公开(公告)日：2008-10-16

申请号：US12214053

申请日：2008-06-16

申请人： Dieter Haerle

发明人： Dieter Haerle

IPC分类号： H03L7/06

CPC分类号： H03L7/0895 ,  H03L7/0812

摘要： A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage.

摘要翻译： 用于锁相环/延迟锁定环的电荷泵通过使用运算放大器将静态相位误差最小化。 运算放大器还可以减轻低电源电压的影响。

公开(公告)号：US07403976B2

公开(公告)日：2008-07-22

申请号：US11323814

申请日：2005-12-29

申请人： David A. Brown

发明人： David A. Brown

IPC分类号： G06F15/167

CPC分类号： H04L47/30 ,  H04L47/70 ,  H04L49/103 ,  H04L49/201 ,  H04L49/252 ,  H04L49/9047

摘要： A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.

摘要翻译： 交换机在共享存储器中包括一个保留的缓冲区池。 保留的缓冲池被保留供出口端口独占使用。 该交换机包括池选择逻辑，其从保留池中选择一个空闲缓冲区，用于存储从入口端口接收的数据以转发到出口端口。 共享内存还包括一个共享的缓冲池。 共享缓冲区池由多个出口端口共享。 池选择逻辑在检测到预留池中没有可用缓冲区时，会选择共享池中的空闲缓冲区。 共享存储器还可以包括缓冲器的多播池。 缓冲区的组播池由多个出口端口共享。 池选择逻辑在检测到从入口端口接收到的IP组播数据包时，选择多播池中的空闲缓冲区。

公开(公告)号：US07336752B2

公开(公告)日：2008-02-26

申请号：US10335535

申请日：2002-12-31

申请人： Peter Vlasenko ,  Dieter Haerle

发明人： Peter Vlasenko ,  Dieter Haerle

IPC分类号： H03D3/24

CPC分类号： H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

公开(公告)号：US07285997B2

公开(公告)日：2007-10-23

申请号：US11699268

申请日：2007-01-29

申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

公开(公告)号：US07190201B2

公开(公告)日：2007-03-13

申请号：US11050644

申请日：2005-02-03

申请人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

发明人： Dieter Haerle ,  Tony Mai ,  Peter Vlasenko

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

摘要翻译： 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

公开(公告)号：US07178001B2

公开(公告)日：2007-02-13

申请号：US10855968

申请日：2004-05-28

申请人： Ian Mes

发明人： Ian Mes

IPC分类号： G06F12/00 ,  G06F1/12 ,  G06F1/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

摘要： An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

摘要翻译： 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出来支持读取数据路径，就可以以任何CAS延迟运行。