发明授权
- 专利标题： Multi-value digital calculating circuits, including multipliers
- 专利标题（中）： 多值数字计算电路，包括乘法器
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申请号： US11018956申请日： 2004-12-20
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公开(公告)号： US07562106B2公开(公告)日： 2009-07-14
- 发明人: Peter Lablans
- 申请人： Peter Lablans
- 申请人地址： US NJ Morristown
- 专利权人： Ternarylogic LLC
- 当前专利权人： Ternarylogic LLC
- 当前专利权人地址： US NJ Morristown
- 代理机构： Diehl Servilla LLC
- 代理商 Glen M. Diehl
- 主分类号： G06F15/00
- IPC分类号： G06F15/00 ; G06F7/52
摘要：
Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.
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