公开(公告)号：US10084593B2

公开(公告)日：2018-09-25

申请号：US15001157

申请日：2016-01-19

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： G06F21/00 ,  H04L9/06

CPC分类号： H04L9/065 ,  H04L9/0643

摘要： A sequence generator implemented on a processor that generates a sequence of signals applies a feedback shift register with feedback. A feedback loop connects at least a first and a second shift register element to last shift register element to a first shift register element of the shift register and includes at least one two-input n-state switching functions that is characterized by non-associative switching functions or switching tables. The sequence generator may be part of a scrambler, an autonomous sequence generator, a hash code generator, a communication device, and a data storage device.

公开(公告)号：US08817928B2

公开(公告)日：2014-08-26

申请号：US13118767

申请日：2011-05-31

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H04L7/00 ,  H04J13/00 ,  H04J13/10 ,  H03K23/54 ,  G06F7/58

CPC分类号： H04L7/0091 ,  G06F7/584 ,  H03K23/54 ,  H04J13/0029 ,  H04J13/0033 ,  H04J13/0074 ,  H04J13/10

摘要： A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism.

摘要翻译： 在接收机上实现的序列发生器与发射机的序列发生器同步。 接收机接收k个n状态符号，其中k> 1且n> 1，其中k个n状态符号中的每一个与发射机处的序列发生器的生成状态相关联。 接收器中的处理器评估产生与接收器的同步状态相关联的n状态符号的n状态表达式。 与n状态表达式相关的系数存储在存储器中，并由处理器检索。 一个实施例中的同步状态是代码跳的一部分。 接收机中的序列发生器可以是数据存储设备和/或打开机构的通信设备的解扰器的一部分。

公开(公告)号：US20130145237A1

公开(公告)日：2013-06-06

申请号：US13757698

申请日：2013-02-01

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03M13/13

CPC分类号： H03M13/13 ,  H03M13/1515 ,  H03M13/1545 ,  H03M13/1575 ,  H03M13/158 ,  H03M13/1585 ,  H03M13/616

摘要： An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p−k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude or error value are determined. The error is corrected by the processor.

摘要翻译： 编码器创建具有p个n状态符号的（p，k，n）n状态码字，其中n个N状态符号是数据符号，n状态符号由n> 2，p> 2的信号表示 和k>（pk）。 在正向和反向的编码器的中间状态被提供在比较的n状态表达式中并在处理器上实现。 通过评估比较的n态表达式，处理器处理表示具有错误的至少一个n状态符号的码字的多个信号。 在接收到符号之后确定表达式的部分结果。 确定错误位置和误差幅度或误差值。 错误由处理器更正。

公开(公告)号：US08103943B2

公开(公告)日：2012-01-24

申请号：US11743893

申请日：2007-05-03

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03M13/00

CPC分类号： H03M13/1575 ,  H03M13/1515 ,  H03M13/159

摘要： Symbol reconstruction methods by applying Galois Field arithmetic to Reed Solomon codewords have been disclosed. Reconstruction methods by applying n-valued reversing logic functions are also provided. A correct codeword can be selected from calculated codewords by comparing a calculated codeword with the Reed-Solomon codeword in error. A correct codeword can also be found by comparing a codeword in error with possible (p,k) codewords. Non Galois Field Reed Solomon coders are disclosed. Methods for correcting symbols in errors that have been identified as being in error are provided. Apparatus that implement the error correction methods are disclosed. Systems, including communication and storage systems that use the disclosed methods are also provided.

摘要翻译： 已经公开了对Reed Solomon码字应用Galois Field算法的符号重构方法。 还提供了通过应用n值反转逻辑功能的重构方法。 可以通过将计算出的码字与错误的Reed-Solomon码字进行比较，从计算出的码字中选择正确的码字。 也可以通过将错误的码字与可能的（p，k）码字进行比较来找到正确的码字。 披露了非伽罗瓦田里德所罗门编码器。 提供了用于校正已被识别为错误的错误中的符号的方法。 公开了实施纠错方法的装置。 还提供了使用所公开方法的系统，包括通信和存储系统。

公开(公告)号：US20110182421A1

公开(公告)日：2011-07-28

申请号：US13081806

申请日：2011-04-07

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H04L9/28

CPC分类号： H04B1/7143

摘要： Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences.

摘要翻译： 公开了根据规则来转移序列元素的方法，其中规则是从伪噪声或伪噪声得到的，如二进制和非二进制序列。 可以通过应用反转规则来恢复转置符号的序列。 通过对其自身应用换位规则创建正交跳跃和转置规则的集合。 正交跳变和转置规则的集合也是从二进制和非二进制Gold序列创建的。

公开(公告)号：US07725779B2

公开(公告)日：2010-05-25

申请号：US11042645

申请日：2005-01-25

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： G06F11/00

CPC分类号： G11B20/00086 ,  G11B20/0021 ,  G11B2220/2537

摘要： Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.

摘要翻译： 公开了用于将加扰的多值数据写入物理介质并从物理介质读取加扰的多值数据的方法和装置。 物理介质可以是光盘。 可以由多值LFSR加扰器执行加扰，并且可以由多值LFSR解扰器执行解扰。 此外，加密的多值数据可以包括同步数据和/或用户数据。 在写入过程中可以使用纠错编码，并且可以在读取过程中使用纠正错误的处理。 此外，公开了用于同步写入物理介质和从物理介质读取的多值数据的方法和装置。 还公开了多值相关方法和装置。

公开(公告)号：US20090172501A1

公开(公告)日：2009-07-02

申请号：US12400900

申请日：2009-03-10

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H03M13/29 ,  G06F11/1012 ,  G06F11/1028 ,  G06F11/1072

摘要： Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated with a matrix for detection of one or more symbols in error and the location of such symbols in error. Symbols in error are reconstructed from symbols not in error, error syndromes and check symbols not in error. Deliberately created errors that can be corrected are used as nuisance errors.

摘要翻译： 方法和装置创建具有n状态检查符号的具有3个或更多个状态中的一个的n状态符号的码字。 检查符号是从独立表达式创建的。 码字与用于检测错误中的一个或多个符号的矩阵以及错误的这种符号的位置相关联。 错误的符号从不是错误的符号重建，错误综合征和检查符号不是错误的。 故意创建的可以纠正的错误被用作妨扰错误。

公开(公告)号：US07355444B2

公开(公告)日：2008-04-08

申请号：US11686542

申请日：2007-03-15

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03K19/00

CPC分类号： H03K19/0002 ,  H03K19/20

摘要： Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.

摘要翻译： 公开了在实现三值和多值功能的电路中使用的门或开关。 门可以是光学的，机械的或电的。 当控制输入为多个状态之一时，或当控制输入为多个状态的两个或多个时，门可以进行或不进行。 还公开了实现三值和多值函数的电路和方法。 还公开了当逻辑表达式不正确实现时可以使用的纠正设计技术。 还提供了使用逆变器和门来实现逻辑表达式的电路。

公开(公告)号：US09100166B2

公开(公告)日：2015-08-04

申请号：US14324217

申请日：2014-07-06

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H04L7/00 ,  H03K23/54 ,  G06F7/58 ,  H04J13/00 ,  H04J13/10

CPC分类号： H04L7/0091 ,  G06F7/584 ,  H03K23/54 ,  H04J13/0029 ,  H04J13/0033 ,  H04J13/0074 ,  H04J13/10

摘要： A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism.

摘要翻译： 在接收机上实现的序列发生器与发射机的序列发生器同步。 接收机接收k个n状态符号，其中k> 1且n> 1，其中k个n状态符号中的每一个与发射机处的序列发生器的生成状态相关联。 接收器中的处理器评估产生与接收器的同步状态相关联的n状态符号的n状态表达式。 与n状态表达式相关的系数存储在存储器中，并由处理器检索。 一个实施例中的同步状态是代码跳的一部分。 接收机中的序列发生器可以是数据存储设备和/或打开机构的通信设备的解扰器的一部分。

公开(公告)号：US08645803B2

公开(公告)日：2014-02-04

申请号：US13103300

申请日：2011-05-09

申请人： Peter Lablans

发明人： Peter Lablans

IPC分类号： H03M13/00

CPC分类号： H03M13/1545 ,  H03M13/1515 ,  H03M13/1585 ,  H03M13/616 ,  H03M13/6502

摘要： An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.

摘要翻译： 编码器创建具有p个n状态符号的（p，k，n）n状态码字，其中n个N状态符号是数据符号，n状态符号由n> 2，p> 2的信号表示 和k>（pk）。 在正向和反向的编码器的中间状态被提供在比较的n状态表达式中并在处理器上实现。 通过评估比较的n态表达式，处理器处理表示具有错误的至少一个n状态符号的码字的多个信号。 在接收到符号之后确定表达式的部分结果。 确定错误位置和误差幅度。 错误由处理器更正。