发明授权
- 专利标题： Performance and area scalable cell architecture technology
- 专利标题（中）： 性能和面积可扩展单元架构技术
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申请号： US11745250申请日： 2007-05-07
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公开(公告)号： US07564077B2公开(公告)日： 2009-07-21
- 发明人: Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
- 申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Ronald O. Neerings; Wade James Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L27/10
- IPC分类号： H01L27/10 ; H01L29/73
摘要：
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
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