摘要:
System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要:
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要:
A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.
摘要:
A current feedback amplifier (12) is provided for controlling a stator winding phase current in a polyphase stator winding, such as a three-phase stator winding (10), of a polyphase direct current motor. The current amplifier (12) includes a first stage current feedback amplifier C (27) and a second stage current feedback amplifier (100) coupled through a switch (101). The first stage current feedback amplifier C (27) detects a stator winding phase current I.sub.AB flowing through a C-coil (15) of the three-phase stator winding (10) and generates an equalized sense current I.sub.senseT in response that is related to I.sub.AB. The equalized sense current I.sub.senseT is generated using a phase trim FET (31) and an adjustable phase trim FET (32). The second stage current feedback amplifier (100) receives I.sub.senseT from the first stage current feedback amplifier C (27) and generates a control signal. This may be done by comparing I.sub.senseT to an amplitude adjusted reference current I.sub.refT. The amplitude adjusted reference current I.sub.refT is generated using an amplitude trim FET (81) and an adjustable amplitude trim FET (82). The second stage current feedback amplifier (100) provides the control signal to a driver circuit for controlling the stator winding phase current. The second stage current feedback amplifier (100) may sequentially or commutatively couple to other first stage current sense amplifiers, such as a first stage current feedback amplifier B (30) or a first stage current feedback amplifier A (28), to control other stator winding phase currents to generate equalized, amplitude adjusted stator winding phase currents.
摘要:
A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.
摘要:
System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.
摘要:
A shock sensor circuitry (26) is provided for processing an input signal generated by a shock sensor (28) in response to the shock sensor (28) detecting a force or shock. The shock sensor circuitry (26) includes a leakage tolerant input amplifier (38) for receiving the input signal, and any leakage currents that may also be provided, and amplifying the input signal to generate an amplified input signal. The leakage tolerant input amplifier (38) provides an ac gain of ten and a dc gain of zero. The shock sensor circuitry (26) also includes a filter and amplification circuit and a window comparator. The filter and amplification circuit filters the amplified input signal and amplifies select frequencies of the amplified input signal to generate a summed signal that is provided to the window comparator and compared to a reference value. The window comparator includes an upper comparator (58), a lower comparator (60), and an output circuit (62) to generate a shock sensor circuitry output signal that indicates whether a shock or force was received at a magnitude greater than the reference value.
摘要:
A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要:
A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.
摘要:
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.