公开(公告)号：US07564077B2

公开(公告)日：2009-07-21

申请号：US11745250

申请日：2007-05-07

申请人： Uming Ko ,  Dharin Shah ,  Senthil Sundaramoorthy ,  Girishankar Gurumurthy ,  Sumanth Gururajarao ,  Rolf Lagerquist ,  Clive Bittlestone

发明人： Uming Ko ,  Dharin Shah ,  Senthil Sundaramoorthy ,  Girishankar Gurumurthy ,  Sumanth Gururajarao ,  Rolf Lagerquist ,  Clive Bittlestone

IPC分类号： H01L27/10 ,  H01L29/73

CPC分类号： G06F17/5072 ,  H01L27/0207 ,  H01L27/11807

摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

摘要翻译： 集成电路。 集成电路包括具有排列成行的布局的区域。 每行可由一对行边界定义。 集成电路还包括多个单元，包括第一组单元。 第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管 。

公开(公告)号：US20070290270A1

公开(公告)日：2007-12-20

申请号：US11745250

申请日：2007-05-07

申请人： Uming Ko ,  Dharin Shah ,  Senthil Sundaramoorthy ,  Girishankar Gurumurthy ,  Sumanth Gururajarao ,  Rolf Lagerquist ,  Clive Bittlestone

发明人： Uming Ko ,  Dharin Shah ,  Senthil Sundaramoorthy ,  Girishankar Gurumurthy ,  Sumanth Gururajarao ,  Rolf Lagerquist ,  Clive Bittlestone

IPC分类号： H01L29/768 ,  G06F17/50

CPC分类号： G06F17/5072 ,  H01L27/0207 ,  H01L27/11807

摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

摘要翻译： 集成电路。 集成电路包括具有排列成行的布局的区域。 每行可由一对行边界定义。 集成电路还包括多个单元，包括第一组单元。 第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管 。