Invention Grant
- Patent Title: Integration process for fabricating stressed transistor structure
- Patent Title (中): 用于制造应力晶体管结构的集成工艺
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Application No.: US11398436Application Date: 2006-04-05
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Publication No.: US07566655B2Publication Date: 2009-07-28
- Inventor: Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
- Applicant: Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Townsend and Townsend and Crew
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.
Public/Granted literature
- US20060270217A1 Integration process for fabricating stressed transistor structure Public/Granted day:2006-11-30
Information query
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