发明授权
- 专利标题： Integration process for fabricating stressed transistor structure
- 专利标题（中）： 用于制造应力晶体管结构的集成工艺
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申请号： US11398436申请日： 2006-04-05
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公开(公告)号： US07566655B2公开(公告)日： 2009-07-28
- 发明人: Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
- 申请人： Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
- 申请人地址： US CA Santa Clara
- 专利权人： Applied Materials, Inc.
- 当前专利权人： Applied Materials, Inc.
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Townsend and Townsend and Crew
- 主分类号： H01L21/44
- IPC分类号： H01L21/44
摘要：
A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.
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