公开(公告)号：US20120285371A1

公开(公告)日：2012-11-15

申请号：US13268093

申请日：2011-10-07

申请人： Chong Ming Lee ,  Andrew Eng Jia Lee

发明人： Chong Ming Lee ,  Andrew Eng Jia Lee

IPC分类号： C30B25/02 ,  C30B25/18

CPC分类号： C30B29/40 ,  C30B25/18 ,  C30B29/406 ,  C30B29/48

摘要： A method for making a flat substrate from incremental-width nanorods includes the steps of: providing a base layer, performing a lateral crystal growth process for a plurality of times, and forming a substrate. The base layer has a plurality of nanorods. Each time the lateral crystal growth process is performed, an additive reagent is added at a different concentration to enable lateral crystal growth and thereby increase the width of each nanorod incrementally. The incremental-width nanorods eventually bond with each other to form a substrate. The substrate may go through an annealing process so as to become a flat substrate.

摘要翻译： 用于从增量宽度纳米棒制造平坦基底的方法包括以下步骤：提供基底层，进行多次的横向晶体生长过程，以及形成基底。 基层具有多个纳米棒。 每次进行横向晶体生长处理时，以不同的浓度添加添加剂试剂以使横向晶体生长，从而逐渐增加每个纳米棒的宽度。 增量宽度的纳米棒最终彼此结合形成底物。 基板可以经过退火工艺以便成为平坦的基板。

公开(公告)号：US20120196452A1

公开(公告)日：2012-08-02

申请号：US13365229

申请日：2012-02-02

申请人： Mihaela Balseanu ,  Michael S. Cox ,  Li-Qun Xia ,  Mei-Yee Shek ,  Jia Lee ,  Vladimir Zubkov ,  Tzu-Fang Huang ,  Rongping Wang ,  Isabelita Roflox ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Michael S. Cox ,  Li-Qun Xia ,  Mei-Yee Shek ,  Jia Lee ,  Vladimir Zubkov ,  Tzu-Fang Huang ,  Rongping Wang ,  Isabelita Roflox ,  Hichem M'Saad

IPC分类号： H01L21/318

CPC分类号： C23C16/345 ,  C23C16/45523 ,  C23C16/56 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823835

摘要： High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400° C., and exposing the deposited silicon nitride film to ultraviolet radiation.

摘要翻译： 沉积层（例如氮化硅层）中的高拉伸应力可以利用单独使用或组合使用的一种或多种技术来实现。 在一个实施例中，可以通过在致孔剂的存在下沉积氮化硅膜来形成具有高拉伸应力的氮化硅膜。 沉积的氮化硅膜可以暴露于选自等离子体或紫外线辐射的至少一种处理以释放致孔剂。 可以使氮化硅膜致密化，使致孔剂释放产生的孔尺寸减小，并且氮化硅膜中的Si-N键变形以在氮化硅膜中产生拉伸应力。 在另一个实施例中，可以通过在低于约400℃的温度下在含氮等离子体的存在下沉积氮化硅膜来增强氮化硅膜中的拉伸应力，并将沉积的氮化硅膜暴露于紫外线 辐射。

公开(公告)号：US07566655B2

公开(公告)日：2009-07-28

申请号：US11398436

申请日：2006-04-05

申请人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

摘要翻译： 工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。 根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。 可以将锗沉积或植入栅极结构中以便于应力控制。

公开(公告)号：US07494938B2

公开(公告)日：2009-02-24

申请号：US11671022

申请日：2007-02-05

申请人： Son V. Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

发明人： Son V. Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 提供了键合相互作用，更多的碳作为甲基端基和比现有技术的SiCOH电介质少的亚甲基-CH 2 - 交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 + CH 2拉伸的峰面积，小于约0.20的SiH拉伸的峰面积，大于约2.0的SiCH 3键合的峰面积以及大于约2.0的峰面积的FTIR光谱，以及 Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

公开(公告)号：US20050242414A1

公开(公告)日：2005-11-03

申请号：US10709320

申请日：2004-04-28

申请人： Matthew Angyal ,  Edward Barth ,  Sanjit Das ,  Charles Davis ,  Habib Hichri ,  William Landers ,  Jia Lee

发明人： Matthew Angyal ,  Edward Barth ,  Sanjit Das ,  Charles Davis ,  Habib Hichri ,  William Landers ,  Jia Lee

IPC分类号： H01L23/58

CPC分类号： H01L23/53295 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interlevel dielectric layer (ILD) comprises a low-k dielectric layer; and a low-k dielectric film, deposited under compressive stress, atop the dielectric layer. The dielectric layer comprises a low-k material, such as an organosilicon glass (OSG) or a SiCOH material. The dielectric film has a thickness, which is 2%-10% of the thickness of the dielectric layer, has a similar chemical composition to the dielectric layer, but has a different morphology than the dielectric layer. The dielectric film is deposited under compressive stress, in situ, at or near the end of the dielectric layer deposition by altering a process that was used to deposit the low-k dielectric layer.

摘要翻译： 层间电介质层（ILD）包括低k电介质层; 以及在压电应力下沉积在电介质层顶上的低k电介质膜。 电介质层包括低k材料，例如有机硅玻璃（OSG）或SiCOH材料。 电介质膜的厚度为电介质层厚度的2％-10％，与电介质层具有相似的化学成分，但具有与电介质层不同的形态。 通过改变用于沉积低k电介质层的工艺，在介电层沉积的结束处或在其附近的压应力下沉积电介质膜。

公开(公告)号：US08331720B2

公开(公告)日：2012-12-11

申请号：US12673504

申请日：2008-08-11

申请人： Kazuo Toraichi ,  Jia Lee ,  Yasuhiro Ohmiya

发明人： Kazuo Toraichi ,  Jia Lee ,  Yasuhiro Ohmiya

IPC分类号： G06K9/40

CPC分类号： H04N1/3935 ,  G06T3/403 ,  G06T2207/20192

摘要： It is possible to provide an image processing device, a method, and a program which can prevent image degradation which occurs when modifying the image magnification. The image processing device includes: an image input unit (10) which performs an image input; an edge direction calculation unit (24) which detects the edge direction contained in an image inputted by the image input unit (10); and an interpolation position decision unit (26), an interpolation object pixel decision unit (28), a first direction interpolation unit (30), and a second direction interpolation unit (32) which perform an interpolation process in the edge direction detected by the edge direction calculation unit (24) on the image inputted by the image input unit (10).

摘要翻译： 可以提供可以防止在修改图像放大率时发生的图像劣化的图像处理装置，方法和程序。 图像处理装置包括：执行图像输入的图像输入单元（10）; 边缘方向计算单元（24），其检测由图像输入单元（10）输入的图像中包含的边缘方向; 以及内插位置决定单元（26），内插对象像素决定单元（28），第一方向内插单元（30）和第二方向内插单元（32），其执行由所述边缘方向检测的边缘方向的内插处理 边缘方向计算单元（24）在图像输入单元（10）输入的图像上。

公开(公告)号：US20120280243A1

公开(公告)日：2012-11-08

申请号：US13279337

申请日：2011-10-24

申请人： Chong-Ming Lee ,  Andrew Eng Jia Lee

发明人： Chong-Ming Lee ,  Andrew Eng Jia Lee

IPC分类号： H01L29/02 ,  H01L21/20

CPC分类号： H01L29/0676 ,  C30B23/025 ,  C30B25/18 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/12

摘要： A fabricating method of a semiconductor substrate is provided. A patterned mask layer is formed on a substrate base. The patterned mask layer includes a plurality of apertures, and each aperture exposes a portion of the substrate base. A plurality of nano-pillars is formed on the substrate base, wherein each nano-pillar is grown on the portion of the substrate base exposed by each aperture. An insulating layer is formed on a sidewall of each nano-pillar. An epitaxial lateral overgrowth process is performed on a top portion of each nano-pillar, so as to form a semiconductor layer on the nano-pillars, wherein the semiconductor layer is exposed by a plurality of gaps disposed between the nano-pillars.

摘要翻译： 提供一种半导体衬底的制造方法。 在基板基底上形成图案化的掩模层。 图案化掩模层包括多个孔，并且每个孔露出基底的一部分。 在衬底基底上形成多个纳米柱，其中每个纳米柱生长在由每个孔暴露的衬底基底的部分上。 在每个纳米柱的侧壁上形成绝缘层。 在每个纳米柱的顶部上进行外延横向过度生长工艺，以便在纳米柱上形成半导体层，其中半导体层被设置在纳米柱之间的多个间隙暴露。

公开(公告)号：US20090026587A1

公开(公告)日：2009-01-29

申请号：US10597038

申请日：2004-01-14

申请人： Matthew Angyal ,  Habib Hichri ,  Henry A. Nye, III ,  Dale McHerron ,  Jia Lee

发明人： Matthew Angyal ,  Habib Hichri ,  Henry A. Nye, III ,  Dale McHerron ,  Jia Lee

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/31633 ,  C23C16/401 ,  C23C16/45523 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274

摘要： A dielectric layer for a semiconductor device having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling. The dielectric layer is made by a process involving continuous variation of dielectric material deposition conditions to provide a dielectric layer having a gradient of dielectric constant.

摘要翻译： 用于半导体器件的电介质层，其具有低的总体介电常数，对半导体衬底的良好的粘附性，以及由于热循环而具有良好的耐开裂性。 通过涉及介电材料沉积条件的连续变化以提供具有介电常数梯度的电介质层的工艺来制造电介质层。

公开(公告)号：US07202564B2

公开(公告)日：2007-04-10

申请号：US10906370

申请日：2005-02-16

申请人： Son Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

发明人： Son Nguyen ,  Sarah L. Lane ,  Jia Lee ,  Kensaku Ida ,  Darryl D. Restaino ,  Takeshi Nogami

IPC分类号： H01L23/48

CPC分类号： H01L21/7682 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3122 ,  H01L21/31633 ,  H01L2221/1047

摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.

摘要翻译： 在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高 键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3/3 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于 约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％ 。

公开(公告)号：US20060270217A1

公开(公告)日：2006-11-30

申请号：US11398436

申请日：2006-04-05

申请人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.