A chip layout is generated based on a quantified fabrication process capability. A minimum required value is selected for a fabrication process capability factor associated with a fabrication process to be performed on a layer sub-region within the chip. Design rules are determined for the layer sub-region within the chip that will enable the selected minimum required value for the fabrication process capability factor associated with the layer sub-region to be satisfied. A layout is then generated for the layer sub-region within the chip using the determined design rules associated with the layer sub-region. Fabrication process capability can be improved by restricting the design rules and generated layouts to a linear design style that requires features defined within the chip to be linear in shape and without bends. The linear design style enables optimization of photolithographic rendering without the need to consider two-dimensional optical effects.