发明授权
US07592669B2 Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel
有权
具有MISFET的半导体器件包括布置在源极/漏极区域和沟道之间的嵌入绝缘膜
- 专利标题: Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel
- 专利标题(中): 具有MISFET的半导体器件包括布置在源极/漏极区域和沟道之间的嵌入绝缘膜
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申请号: US11776380申请日: 2007-07-11
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公开(公告)号: US07592669B2公开(公告)日: 2009-09-22
- 发明人: Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
- 申请人: Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Antonelli, Terry, Stout & Kraus, LLP.
- 优先权: JP2003-384654 20031114
- 主分类号: H01L29/78
- IPC分类号: H01L29/78
摘要:
With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
公开/授权文献
- US20080258236A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 公开/授权日:2008-10-23
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