Invention Grant
- Patent Title: Adjustable digital lock detector
- Patent Title (中): 可调数字锁定检测器
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Application No.: US11861260Application Date: 2007-09-25
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Publication No.: US07595672B2Publication Date: 2009-09-29
- Inventor: Tse-Peng Chen
- Applicant: Tse-Peng Chen
- Applicant Address: TW Taipei
- Assignee: RichWave Technology Corp.
- Current Assignee: RichWave Technology Corp.
- Current Assignee Address: TW Taipei
- Agent Winston Hsu
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
An adjustable digital lock detector for a phase-locked loop (PLL) has a variable counter for outputting an output signal corresponding to a first clock signal, a target count number signal, and a count number offset signal, a latch for sampling the output signal of the variable counter and outputting a latch output signal according to a result of sampling the output signal, a lead/lag detector for receiving the latch output signal and outputting the count number offset signal according to a predetermined state of the latch output signal, and an arbiter for receiving the latch output signal and outputting an arbiter output signal according to the latch output signal and a second clock signal.
Public/Granted literature
- US20090079479A1 ADJUSTABLE DIGITAL LOCK DETECTOR Public/Granted day:2009-03-26
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